Peripheral Interrupt Trigger Input Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Architecture
Once a particular interrupt trigger sets a channel's PERINTFLG bit, the bit stays pending until the priority
logic of the state machine starts the burst transfer for that channel. Once the burst transfer starts, the flag
is cleared. If a new interrupt trigger is generated while a burst is in progress, the burst will complete before
responding to the new interrupt trigger (after proper prioritization). If a third interrupt trigger occurs before
the pending interrupt is serviced, an error flag is set in the CONTROL.CHx[OVRFLG] bit. If a peripheral
interrupt trigger occurs at the same time as the latched flag is being cleared, the peripheral interrupt
trigger has priority and the PERINTFLG will remain set.
Figure 11-2 shows a diagram of the trigger select circuit. See the MODE.CHx[PERINTSEL] bit field
description for the complete list of peripheral interrupt trigger sources.
Clear interrupt
DMA
channel x
processing
Peripheral
logic
Table 11-1 shows the interrupt trigger source options that are available for each channel.
914
C28 Direct Memory Access (DMA) Module
Figure 11-2. Peripheral Interrupt Trigger Input Diagram
CONTROL.CHx[PERINTFLG]
Clear
Int
Latch
MODE.CHx
[PERINTE]
Set
Copyright © 2012–2019, Texas Instruments Incorporated
MODE.CHx
[PERINTSEL]
CONTROL.CHx
[PERINTCLR]
CONTROL.CHx
[PERINTFRC]
Clear peripheral interrupt
trigger flag if appropriate
SPRUH22I – April 2012 – Revised November 2019
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None
ADCINT1
ADCINT2
.
.
.
EPWM8SOCB
EPWM9SOCA
EPWM9SOCB