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24.8.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 in the Cortex-
M3 Peripherals chapter. Software can disable execution of the handlers for these faults (see
SYSHNDCTRL in the Cortex-M3 Peripherals chapter.
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another fault
handler as described in
In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority
escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
•
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault
occurs because a fault handler cannot preempt itself because it must have the same priority as the
current priority level.
•
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation
happens because the handler for the new fault cannot preempt the currently executing fault handler.
•
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
•
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate
to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
24.8.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the
fault address register indicates the address accessed by the operation that caused the fault, as shown in
Table
24-20.
Handler
Hard fault
Memory management fault
Bus fault
Usage fault
24.8.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers.
When the processor is in the lockup state, it does not execute any instructions. The processor remains in
lockup state until it is reset or an NMI occurs.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to
leave the lockup state.
24.9 Power Management
The Cortex-M3 processor sleep mode and deep-sleep mode reduces power consumptions:
•
Sleep mode stops the processor clock.
•
Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
SPRUH22I – April 2012 – Revised November 2019
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Section
24.7.
Table 24-20. Fault Status and Fault Address Registers
Status Register Name
Hard Fault Status (HFAULTSTAT)
Memory Management Fault Status
(MFAULTSTAT)
Bus Fault Status (BFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
Copyright © 2012–2019, Texas Instruments Incorporated
Fault Handling
Address Register Name
-
Memory Management Fault Address
(MMADDR)
Bus Fault Address (FAULTADDR)
-
Cortex-M3 Processor
1593
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