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Functional Description
19.3.4 DMA Operation
The Ethernet peripheral provides request signals to the μDMA controller and has a dedicated channel for
transmit and one for receive. The request is a single type for both channels. Burst requests are not
supported. The RX channel request is asserted when a packet is received while the TX channel request is
asserted when the transmit FIFO becomes empty.
No special configuration is needed to enable the ethernet peripheral for use with the μDMA controller.
Because the size of a received packet is not known until the header is examined, it is best to set up the
initial μDMA transfer to copy the first 4 words including the packet length plus the Ethernet header from
the RX FIFO when the RX request occurs. The μDMA causes an interrupt when this transfer is complete.
Upon entering the interrupt handler, the packet length in the FIFO and the Ethernet header are in a buffer
and can be examined. Once the packet length is known, then another μDMA transfer can be set up to
transfer the remaining received packet payload from the FIFO into a buffer. This transfer should be
initiated by software. Another interrupt occurs when this transfer is done.
Even though the TX channel generates a TX empty request, the recommended way to handle μDMA
transfers for transmitting packets is to set up the transfer from the buffer containing the packet to the
transmit FIFO, and then to initiate the transfer with a software request. An interrupt occurs when this
transfer is complete. For both channels, the "auto-request" transfer mode should be used. See the Micro
Direct Memory Access (μDMA) chapter for more details about programming the μDMA controller.
19.4 Initialization and Configuration
The following sections describe the hardware and software configuration required to set up the Ethernet
MAC.
19.4.1 Software Configuration
To use the Ethernet MAC, it must be enabled by setting the EMAC0 bit in the RCGC2 register. In addition,
the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control
module. To find out which GPIO port to enable, refer to the GPIO chapter.
The following steps can then be used to configure the Ethernet MAC for basic operation.
1. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a
100-MHz system clock, the MACDIV value should be 0x13 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a
value of 0x16.
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using a
value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL
registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register to
initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available for the
next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP) register
to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. To
ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare
the number of bytes received to the Length field from the frame to determine when the packet has
been completely read.
1386
M3 Ethernet Media Access Controller (EMAC)
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
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