Wirmode Registers; Master Subsystem Wait-In-Reset (Mwir) Register; C28 Wait-In-Reset (Cwir) Register; Master Subsystem Wait-In-Reset (Mwir) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.13.4 WIRMODE Registers

1.13.4.1 Master Subystem Wait-In-Reset (MWIR) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-67. Master Subsystem Wait-In-Reset (MWIR) Register Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUH22I – April 2012 – Revised November 2019

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Figure 1-56. Master Subsystem Wait-In-Reset (MWIR) Register

Re-sample EMU0 and EMU1 Pins

Has no effect

Forces a re-sample of the EMU0 and EMU1 pins and the values will be latched in the EMU0/EMU1

Latched State of EMU1 Pin

The state of EMU1 pin is latched on reset (XRS AND POR) or when the SAMPLE bit is triggered.

Reading this bit will give the state of the EMU1 pin on reset or when sampled.

Has no effect

Forces the bit to "1"

Latched State of EMU0 Pin

The state of EMU0 pin is latched on reset (XRS AND POR) or when the SAMPLE bit is triggered.

Reading this bit will give the state of the EMU0 pin on reset or when sampled.

Has no effect

Forces the bit to "1"

Figure 1-57. C28 Wait-In-Reset (CWIR) Register

Table 1-68. C28 Wait-In-Reset (CWIR) Register Field Descriptions

Re-sample EMU0 and EMU1 Pins

Has no effect

Forces a r-sample of the EMU0 and EMU1 pins and the values will be latched in the EMU0/EMU1

Latched State of EMU1 Pin

The state of EMU1 pin is latched on reset (XRS AND POR) or when the SAMPLE bit is triggered.

Reading this bit will give the state of the EMU1 pin on reset or when sampled.

Has no effect

Forces the bit to "1"

System Control Registers

System Control and Interrupts

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