Usb Control And Status Endpoint 0 Low Register (Usbcsrl0) In Otg B/Device Mode; Usb Control And Status Endpoint 0 Low Register (Usbcsrl0) In Otg B/Device Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 18-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in OTG B/Device

LEGEND: R/W = Read/Write; -n = value after reset

SPRUH22I – April 2012 – Revised November 2019

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Table 18-38. USB Control and Status Endpoint 0 Low Register

(USBCSRL0) in OTG B/Device Mode Field Descriptions

Setup End Clear

Writing a 1 to this bit clears the SETEND bit.

Writing a 1 to this bit clears the RXRDY bit.

Terminates the current transaction and transmits the STALL handshake.

This bit is cleared automatically after the STALL handshake is transmitted.

A control transaction has not ended or ended after the DATAEND bit was set.

A control transaction has ended before the DATAEND bit has been set. The EP0 bit in the USBTXIS

This bit is cleared by writing a 1 to the SETENDC bit.

Set this bit in the following situations:

• When setting TXRDY for the last data packet

• When clearing RXRDY after unloading the last data packet

• When setting TXRDY for a zero-length data packet

This bit is cleared automatically.

Endpoint Stalled. Software must clear this bit.

A STALL handshake has not been transmitted.

A STALL handshake has been transmitted.

Transmit Packet Ready. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just

TXRDY is set, an OUT packet is sent.

No transmit packet is ready.

Software sets this bit after loading an IN data packet into the TX FIFO. The EP0 bit in the USBTXIS

Receive Packet Ready.

No receive packet has been received.

A data packet has been received. The EP0 bit in the USBTXIS register is also set in this situation.

This bit is cleared by writing a 1 to the RXRDYC bit.

M3 Universal Serial Bus (USB) Controller

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