Double-Buffered Wut And Txshf - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Enhanced SCI Module Overview
a block start.
13.1.1.5.2 Block Start Signal
There are two ways to send a block-start signal:
1. Method 1: Deliberately leave an idle time of ten bits or more by delaying the time between the
transmission of the last frame of data in the previous block and the transmission of the address frame
of the new block.
2. Method 2: The SCI port first sets the TXWAKE bit (SCICTL1, bit 3) to 1 before writing to the
SCITXBUF register. This sends an idle time of exactly 11 bits. In this method, the serial
communications line is not idle any longer than necessary. (A don't care byte has to be written to
SCITXBUF after setting TXWAKE, and before sending the address, so as to transmit the idle time.)
13.1.1.5.3 Wake-UP Temporary (WUT) Flag
Associated with the TXWAKE bit is the wake-up temporary (WUT) flag. WUT is an internal flag, double-
buffered with TXWAKE. When TXSHF is loaded from SCITXBUF, WUT is loaded from TXWAKE, and the
TXWAKE bit is cleared to 0. This arrangement is shown in
A WUT = wake-up temporary
Sending a Block Start Signal
To send out a block-start signal of exactly one frame time during a sequence of block transmissions:
1. Write a 1 to the TXWAKE bit.
2. Write a data word (content not important: a don't care) to the SCITXBUF register (transmit data buffer)
to send a block-start signal. (The first data word written is suppressed while the block-start signal is
sent out and ignored after that.) When the TXSHF (transmit shift register) is free again, SCITXBUF
contents are shifted to TXSHF, the TXWAKE value is shifted to WUT, and then TXWAKE is cleared.
Because TXWAKE was set to a 1, the start, data, and parity bits are replaced by an idle period of 11
bits transmitted following the last stop bit of the previous frame.
3. Write a new address value to SCITXBUF
A don't-care data word must first be written to register SCITXBUF so that the TXWAKE bit value can
be shifted to WUT. After the don't-care data word is shifted to the TXSHF register, the SCITXBUF (and
TXWAKE if necessary) can be written to again because TXSHF and WUT are both double-buffered.
13.1.1.5.4 Receiver Operation
The receiver operates regardless of the SLEEP bit. However, the receiver neither sets RXRDY nor the
error status bits, nor does it request a receive interrupt until an address frame is detected.
13.1.1.6 Address-Bit Multiprocessor Mode
In the address-bit protocol (ADDR/IDLE MODE bit=1), frames have an extra bit called an address bit that
immediately follows the last data bit. The address bit is set to 1 in the first frame of the block and to 0 in all
other frames. The idle period timing is irrelevant (see
986
C28 Serial Communications Interface (SCI)
Figure 13-5. Double-Buffered WUT and TXSHF
Transmit buffer (SCITXBUF)
TXWAKE
1
WUT
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Figure 13-5.
8
TXSHF
Figure 13-6).
SPRUH22I – April 2012 – Revised November 2019
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