Details Of The Counter And Synchronization Block - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 8-7. Details of the Counter and Synchronization Block

ECCTL2[SYNCI_EN]

8.4.5 CAP1-CAP4 Registers

These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a time-

stamp) when their respective LD inputs are strobed.

Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this

bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.

CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.

CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and

CAP2 during APWM operation.

8.4.6 Interrupt Control

An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events (CTR =

PRD, CTR = CMP).

A counter overflow event (FFFFFFFF->00000000) is also provided as an interrupt source (CTROVF).

The capture events are edge and sequencer qualified (ordered in time) by the polarity select and Mod4

gating, respectively.

One of these events can be selected as the interrupt source (from the eCAPx module) going to the PIE.

Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR=PRD, CTR=CMP) can be

generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event

sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains

the global interrupt flag bit (INT). An interrupt pulse is generated to the PIE only if any of the interrupt

events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must clear the

global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any other

interrupt pulses are generated. You can force an interrupt event via the interrupt force register (ECFRC).

This is useful for test purposes.

SPRUH22I – April 2012 – Revised November 2019

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(counter 32b)

ECCTL2[SWSYNC]

ECCTL2[SYNCOSEL]

C28 Enhanced Capture (eCAP) Module

Capture Mode Description

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