Interrupt 0-133 Priority (Pri0-Pri33) Registers, Offset 0X400-0X484; Software Trigger Interrupt (Swtrig) Register, Offset 0Xf00; Interrupt 0-133 Priority (Pri0-Pri33) Registers; Interrupt 0-133 Priority (Pri0-Pri33) Registers Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

NVIC Register Descriptions

25.5.26 Interrupt 0-133 Priority (PRI0-PRI33) Registers, offset 0x400-0x484

The Interrupt 0-133 Priority (PRI0-PRI33) registers provide 3-bit priority fields for each interrupt. These
registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as
follows:
PRIn Register Bit Field
Bits 31:29
Bits 23:21
Bits 15:13
Bits 7:5
See the Cortex-M3 Processor chapter for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in
the Application Interrupt and Reset Control (APINT) register indicates the position of the binary point that
splits the priority and subpriority fields .
Note: This register can only be accessed from privileged mode.
31 29 28
INTD
R/W-0
15 13 12
INTB
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-36. Interrupt 0-133 Priority (PRI0-PRI33) Registers Field Descriptions
Bit Field
31-29 INTD
28-24 Reserved
23-21 INTC
20-16 Reserved
15-13 INTB
12-8 Reserved
7-5 INTA
4-0 Reserved

25.5.27 Software Trigger Interrupt (SWTRIG) Register, offset 0xF00

The Software Trigger Interrupt (SWTRIG) Register is described below. Writing an interrupt number to the
SWTRIG register generates a Software Generated Interrupt (SGI). See the Cortex-M3 Processor chapter
for interrupt assignments.
1626
Cortex-M3 Peripherals
Figure 25-30. Interrupt 0-133 Priority (PRI0-PRI33) Registers
Reserved
R-0
Reserved
R-0
Value Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number
of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the
priority of the corresponding interrupt.
Reserved
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number
of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the
priority of the corresponding interrupt.
Reserved
Interrupt Priority for Interrupt [4n+1
This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number
of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the
priority of the corresponding interrupt.
Reserved
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of
the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority
of the corresponding interrupt.
Reserved
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Interrupt
Interrupt [4n+3]
Interrupt [4n+2]
Interrupt [4n+1]
Interrupt [4n]
24 23 21
INTC
R/W-0
8 7 5
INTA
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
20
Reserved
R-0
4
Reserved
R-0
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