Mode Register (Mode); Mode Register (Mode) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions
11.8.6 Mode Register (MODE) — EALLOW Protected
The mode register (MODE) is shown in
15 14
CHINTE DATASIZE
R/W-0 R/W-0
7 6
OVRINTE Reserved
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15 CHINTE
14 DATASIZE
13-12 Reserved
11 CONTINUOUS
10 ONESHOT
9 CHINTMODE
8 PERINTE
7 OVRINTE
6-5 Reserved
932
C28 Direct Memory Access (DMA) Module
Figure 11-13
Figure 11-13. Mode Register (MODE)
13 12
Reserved
R/W-0
5 4
R-0
Table 11-8. Mode Register (MODE) Field Descriptions
Value Description
Channel Interrupt Enable Bit: This bit enables/disables the respective DMA channel interrupt
to the CPU (via the PIE).
0 Interrupt disabled
1 Interrupt enabled
Data Size Mode Bit: This bit selects if the DMA channel transfers 16-bits or 32-bits of data at a
time.
0 16-bit data transfer size
1 32-bit data transfer size
NOTE: Regardless of the value of this bit all of the registers in the
DMA refer to 16-bit words. The only effect this bit causes
is whether the databus width is 16 or 32 bits.
It is up to you to configure the pointer step increment and
size to accommodate 32-bit data transfers. See section
Section 11.6
Reserved
Continuous Mode Bit: If this bit is set to 1, then DMA re-initializes when TRANSFER_COUNT
is zero and waits for the next interrupt event trigger. If this bit is 0, then the DMA stops and
clears the RUNSTS bit to 0.
One Shot Mode Bit: If this bit is set to 1, then subsequent burst transfers occur without
additional event triggers after the first event trigger. If this bit is 0 then only one burst transfer
is performed per event trigger.
Note: High-priority mode and One-shot mode may not be used at the same time on CH1.
Channel Interrupt Generation Mode Bit: This bit specifies when the respective DMA channel
interrupt should be generated to the CPU (via the PIE).
0 Generate interrupt at beginning of new transfer
1 Generate interrupt at end of transfer.
Peripheral Interrupt Trigger Enable Bit: This bit enables/disables the selected peripheral
interrupt trigger to the DMA.
0 Interrupt trigger disabled. Neither the selected peripheral nor software can start a DMA burst.
1 Interrupt trigger enabled.
Overflow Interrupt Enable: This bit when set to 1 enables the DMA to generate an interrupt
when an overflow event is detected.
0 Overflow interrupt disabled
1 Overflow interrupt enabled
An overflow interrupt is generated when the PERINTFLG is set and another interrupt event
occurs. The PERINTFLG being set indicates a previous peripheral event is latched and has
not been serviced by the DMA.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
and described in Table
11 10
CONTINUOUS ONESHOT
R/W-0 R/W-0
PERINTSEL
R/W-0
for details.
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
11-8.
9 8
CHINTMODE PERINTE
R/W-0 R/W-0
0
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