Host-Bus Write Cycle, Mode = 0X1, Wrhigh = 0, Rdhigh = 0, Alehigh = 1; Alehigh - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 17-9. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0, ALEHIGH = 1
ALE
( )
EPI0S30
CS
(EPI0S30)
WR
( )
EPI0S29
RD/OE
( )
EPI0S28
BSEL0/
a
BSEL1
Address
Data
a
BSEL0 and BSEL1 are available in Host-Bus16 mode only.
Figure 17-10 shows a write cycle with the address and data signals multiplexed (MODE field is 0x0 in the
EPIHBnCFG register). A read cycle would look similar, with the RD strobe being asserted along with CS
and data being latched on the rising edge of RD.
Figure 17-10. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0,
ALE
( )
EPI0S30
CS
( )
EPI0S30
WR
( )
EPI0S29
RD/ OE
( )
EPI0S28
a
BSEL0/ BSEL1
Address
(high order , non-muxed)
Muxed
Address/Data
a
BSEL0 and BSEL1 are available in Host-Bus16 mode only .
When using ALE with dual CS configuration (CSCFGEXT bit is 0 and the CSCFG field is 0x3 in the
EPIHBnCFG2 register) or quad chip select (CSCFGEXT bit is 1 and CSCSFG is 0x2), the appropriate CS
signal is asserted at the same time as ALE, as shown in
SPRUH22I – April 2012 – Revised November 2019
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RDHIGH = 0, ALEHIGH = 1
Address
Copyright © 2012–2019, Texas Instruments Incorporated
Data
Data
Figure 17-11.
External Peripheral Interface (EPI)
Host Bus Mode
1213