Table of Contents
Advertisement
www.ti.com
13.3.5 SCI Control Register 2 (SCICTL2)
SCICTL2 enables the receive-ready, break-detect, and transmit-ready interrupts as well as transmitter-
ready and -empty flags.
7
6
TXRDY
TX EMPTY
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
7
TXRDY
6
TX EMPTY
5-2
Reserved
1
RX/BK INT ENA
0
TX INT ENA
13.3.6 SCI Receiver Status Register (SCIRXST)
SCIRXST contains seven bits that are receiver status flags (two of which can generate interrupt requests).
Each time a complete character is transferred to the receiver buffers (SCIRXEMU and SCIRXBUF), the
status flags are updated.
Figure 13-17. SCI Receiver Status Register (SCIRXST) — Address 7055h
7
6
RX ERROR
RXRDY
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 13-16. SCI Control Register 2 (SCICTL2) — Address 7054h
5
Table 13-12. SCI Control Register 2 (SCICTL2) Field Descriptions
Value
Description
Transmitter buffer register ready flag. When set, this bit indicates that the transmit data buffer
register, SCITXBUF, is ready to receive another character. Writing data to the SCITXBUF
automatically clears this bit. When set, this flag asserts a transmitter interrupt request if the
interrupt-enable bit, TX INT ENA (SCICTL2.0), is also set. TXRDY is set to 1 by enabling the SW
RESET bit (SCICTL1.5) or by a system reset.
0
SCITXBUF is full
1
SCITXBUF is ready to receive the next character
Transmitter empty flag. This flag's value indicates the contents of the transmitter's buffer register
(SCITXBUF) and shift register (TXSHF). An active SW RESET (SCICTL1.5), or a system reset,
sets this bit. This bit does not cause an interrupt request.
0
Transmitter buffer or shift register or both are loaded with data
1
Transmitter buffer and shift registers are both empty
Receiver-buffer/break interrupt enable. This bit controls the interrupt request caused by either the
RXRDY flag or the BRKDT flag (bits SCIRXST.6 and .5) being set. However, RX/BK INT ENA does
not prevent the setting of these flags.
0
Disable RXRDY/BRKDT interrupt
1
Enable RXRDY/BRKDT interrupt
SCITXBUF-register interrupt enable. This bit controls the interrupt request caused by setting the
TXRDY flag bit (SCICTL2.7). However, it does not prevent the TXRDY flag from being set, which
indicates SCITXBUF is ready to receive another character.
0
Disable TXRDY interrupt
1
Enable TXRDY interrupt
In non-FIFO mode, a dummy (or a valid) data has to be written to SCITXBUF for the first transmit
interrupt to occur. This is the case when you enable the transmit interrupt for the first time and also
when you re-enable (disable and then enable) the transmit interrupt. If TXINTENA is enabled after
writing the data to SCITXBUF, it will not generate an interrupt.
Figure 13-18
shows the relationships between several of the register's bits.
5
4
BRKDT
FE
R-0
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
2
Reserved
R-0
3
2
OE
PE
R-0
R-0
C28 Serial Communications Interface (SCI)
SCI Registers
1
0
RX/BK INT
TX INT ENA
ENA
R/W-0
R/W-0
1
0
RXWAKE
Reserved
R-0
R-0
999
Advertisement
Chapters
Table of Contents
