Interrupt 96-127 Clear Pending (Unpend3) Register, Offset 0X28C; Interrupt 96-127 Clear Pending (Unpend3) Register; Interrupt 96-127 Clear Pending (Unpend3) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

NVIC Register Descriptions

25.5.19 Interrupt 96-127 Clear Pending (UNPEND3) Register, offset 0x28C

The Interrupt 96-127 Clear Pending (UNPEND3) register shows which interrupts are pending and removes
the pending state from interrupts. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127.
See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-29. Interrupt 96-127 Clear Pending (UNPEND3) Register Field Descriptions
Bit Field
31-0 INT
1622
Cortex-M3 Peripherals
Figure 25-23. Interrupt 96-127 Clear Pending (UNPEND3) Register
R/W-0
Value Description
Interrupt Clear Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in
the PEND2 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the
active state of the corresponding interrupt
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INT
SPRUH22I – April 2012 – Revised November 2019
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