Dma Peripheral Identification 1 (Dmaperiphid1), Offset 0Xfe4; Dma Peripheral Identification 2 (Dmaperiphid2), Offset 0Xfe8; Dma Peripheral Identification 3 (Dmaperiphid3), Offset 0Xfec; Dma Peripheral Identification 0 (Dmaperiphid0) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 16-32. DMA Peripheral Identification 0 (DMAPeriphID0) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

16.7.24 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4

The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
Figure 16-33. DMA Peripheral Identification 1 (DMAPeriphID1) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-39. DMA Peripheral Identification 1 (DMAPeriphID1) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 PID1

16.7.25 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8

The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
Figure 16-34. DMA Peripheral Identification 2 (DMAPeriphID2) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-40. DMA Peripheral Identification 2 (DMAPeriphID2) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 PID2

16.7.26 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC

The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
Figure 16-35. DMA Peripheral Identification 3 (DMAPeriphID3) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Reserved
R-0
Reserved
R-0
Value Description
Reserved
µDMA Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
Reserved
R-0
Value Description
Reserved
µDMA Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
µDMA Register Descriptions
8 7
PID0
R-30
8 7
PID1
R-B2
8 7
PID2
R-0B
8 7
PID3
R-0
M3 Micro Direct Memory Access ( µDMA)
0
0
0
0
1187