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The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case, a
Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the BADCRC
bit in the MACRCTL register.
In normal operating mode, the receiver accepts only those frames that have a destination address that
matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0) and Ethernet
MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can also be configured for
Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the MACRCTL register.
19.3.1.5 Packet Timestamps
Some applications require a very precise clock for time stamping samples or triggering events. The IEEE
Precision Time Protocol (PTP), or IEEE-1588, provides a mechanism for synchronizing clocks across an
Ethernet to sub-microsecond precision. The accuracy of the PTP clock depends greatly upon the accuracy
of timestamps of the PTP Ethernet packets. In a software-only PTP solution, there can be jitter in the
Ethernet packet timestamps, resulting in a less precise PTP clock on the target. In some devices,
General-Purpose Timer 3 (GPT3) can be used in conjunction with the Ethernet MAC Timer Support
(MACTS) register to provide a more accurate timestamp for Ethernet packets.
This feature is enabled by setting the TSEN bit in the MACTS register. Note that when this feature is
enabled, GPT3 must be dedicated to the Ethernet MAC. GPT3 must be configured to 16-bit edge capture
mode. This is described in the GP Timers chapter. Timer A of GPT3 stores the transmit time, and Timer B
stores the receive time. One other General-Purpose Timer can be set up as a 16-bit free-running timer to
synchronize the receiver and transmitter timers and provide a timestamp with which to compare the
timestamps stored in GPT3. The enet_ptpd example in the controlSUITE™ software package provides a
sample PTP application that illustrates both software-only time stamping as well the use of the GPT3 and
MACTS register for more accurate timestamps. This example supports version 1 of the IEEE-1588
protocol, but Concerto™ microcontrollers support both versions 1 and 2.
19.3.1.6 Ethernet MAC Address
The Ethernet MAC address consists of 6 octets that uniquely identify the Ethernet MAC. The MAC
address is split up into EMACID0, which should be stored at OTP location 0x680810 and EMACID1, which
should be stored at OTP location 0x680814. See the example below for how to store the MAC address
into OTP.
MAC Address of 12-34-56-78-9A-BC should be stored as:
•
EMACID0: 0x00563412 (stored at 0x681010)
•
EMACID1: 0x00BC9A78 (stored at 0x681014)
The top byte of each EMACID location is 0x00. Only the lower 3 bytes of each EMACID location are
used as shown above.
19.3.2 Internal MII Operation
For the MII management interface to function properly, the internal clock must be divided down from the
system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider
(MACMDV) register contains the divider used for scaling down the system clock.
19.3.3 Interrupts
The Ethernet MAC can generate an interrupt for one or more of the following conditions:
•
A frame has been received into an empty RX FIFO
•
A frame transmission error has occurred
•
A frame has been transmitted successfully
•
A frame has been received with inadequate room in the RX FIFO (overrun)
•
A frame has been received with one or more error conditions (for example, FCS failed)
•
An MII management transaction between the MAC and PHY layers has completed
SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
Functional Description
M3 Ethernet Media Access Controller (EMAC)
1385
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