Epi Host-Bus 16 Configuration 4 (Epihb16Cfg4), Offset 0X30C; Epi Host-Bus 16 Configuration 4 Register (Epihb16Cfg4) [Offset 0X30C]; Epi Host-Bus 16 Configuration 4 Register (Epihb16Cfg4) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.11.28 EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C

NOTE: The MODE field in the EPICFG register determines which configuration is enabled. For
EPIHB16CFG4 to be valid, the MODE field must be 0x3.
Figure 17-55. EPI Host-Bus 16 Configuration 4 Register (EPIHB16CFG4) [offset 0x30C]
31
Reserved
R-0
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-41. EPI Host-Bus 16 Configuration 4 Register (EPIHB16CFG4) Field Descriptions
Bit Field
31-22 Reserved
21 WRHIGH
20 RDHIGH
19 ALEHIGH
18-17 Reserved
16 BURST
15-8 Reserved
7-6 WRWS
5-2 Reserved
SPRUH22I – April 2012 – Revised November 2019
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22
R-0
Value Description
Reserved
CS3 WRITE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2 .
0 The WRITE strobe for CS3 accesses is WR (active Low).
1 The WRITE strobe for CS3 accesses is WR (active High).
CS3 READ Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0 The READ strobe for CS3 accesses is RD (active Low).
1 The READ strobe for CS3 accesses is RD (active High).
CS3 ALE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0 The address latch strobe for CS3 accesses is ADV (active Low).
1 The address latch strobe for CS3 accesses is ALE (active High).
Reserved
CS3 Burst Mode
Burst mode must be used with an ALE, which is configured by programming the CSCFG and
CSCFGEXT fields in the EPIHB16CFG2 register. Burst mode must be used in ADMUX, which is set
by the MODE field in EPIHB16CFG4.
Note: Burst mode is optimized for word-length accesses.
0 Burst mode is disabled
1 Burst mode is enabled for CS3
Reserved
CS3 Write Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS3 accesses (the address phase is not affected).
The effect is to delay the rising edge of WR (or the falling edge of WR. Each wait state adds two
EPI clock cycles to the access time. The WRWSM bit in the EPIHB16TIME4 register can decrease
the number of wait states by one EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB16CFG2 register. This field is not applicable in BURST mode.
0x0 Active WR is 2 EPI clocks
0x1 Active WR is 4 EPI clocks
0x2 Active WR is 6 EPI clocks
0x3 Active WR is 8 EPI clocks
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
21 20
WRHIGH RDHIGH
R/W-0 R/W-0
8 7 6 5
WRWS
R/W-0
Register Descriptions
19 18 17
ALEHIGH Reserved
R/W-1 R-0
2 1
Reserved MODE
R-0 R/W-0
External Peripheral Interface (EPI)
16
BURS
T
R/W-0
0
1267