Deep Sleep Mode Clock Gating Control Register 1 (Dcgc1); Deep Sleep Mode Clock Gating Control Register 1 (Dcgc1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.13.7.18 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)

Figure 1-110. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
31 30
EPI
23
Reserved
15 14
Reserved I2C1
R-0 R/W-0
7 6
SSI3 SSI2
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-121. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Field Descriptions
Bit Field
31 Reserved
30 EPI
29-20 Reserved
19 TIMER3
18 TIMER2
17 TIMER1
16 TIMER0
15 Reserved
14 I2C1
13 Reserved
12 I2C0
11-8 Reserved
7 SSI3
SPRUH22I – April 2012 – Revised November 2019
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29
20
R-0
13 12
Reserved I2C0
R-0 R/W-0
5 4
SSI1 SSI0
R/W-0 R/W-0
Value Description
Reserved
EPI Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the EPI module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
GPT3 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the TIMER3 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPT2 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the TIMER2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPT1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the TIMER1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPT0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the TIMER0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
I2C1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the I2C1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
I2C0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the I2C0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
SSI3 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the SSI3 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Copyright © 2012–2019, Texas Instruments Incorporated
19 18
TIMER3 TIMER2
R/W-0 R/W-0
11
Reserved
R-0
3 2
UART3 UART2
R/W-0 R/W-0
System Control and Interrupts
System Control Registers
24
17 16
TIMER1 TIMER0
R/W-0 R/W-0
8
1 0
UART1 UART0
R/W-0 R/W-0
233