Lx Dedram Configuration Register 1 (Lxdrcr1); Lx Dedram Configuration Register 1 (Lxdrcr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.3 C28x RAM Configuration Registers
5.2.3.1

Lx DEDRAM Configuration Register 1 (LxDRCR1)

31
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-46. Lx DEDRAM Configuration Register 1 (LxDRCR1) Field Descriptions
Bit Field
31-11 Reserved
10 CPUWRPROTL1
9 Reserved
8 FETCHPROTL1
7-3 Reserved
2 CPUWRPROTL0
1 Reserved
0 FETCHPROTL0
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-41. Lx DEDRAM Configuration Register 1 (LxDRCR1)
Reserved
R-0
Reserved
R-0
Value Description
Reserved
CPU Write Protection L1
0 C28x CPU write allowed to L1 RAM block.
1 C28x CPU write not allowed to L1 RAM block.
Reserved
CPU Fetch Protection L1
0 C28x CPU Fetch allowed from L1 RAM block.
1 C28x CPU Fetch not allowed from L1 RAM block.
Reserved
CPU Write Protection L0
0 C28x CPU write allowed to L0 RAM block.
1 C28x CPU write not allowed to L0 RAM block.
Reserved
CPU Fetch Protection L0
0 C28x CPU Fetch allowed from L0 RAM block.
1 C28x CPU Fetch not allowed from L0 RAM block.
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Reserved
R-0
11 10
CPUWRPROTL
1
R/W-0
3 2
CPUWRPROTL
0
R/W-0
RAM Control Module Registers
16
9 8
Reserved FETCHPROTL
1
R-0 R/W-0
1 0
Reserved FETCHPROTL
0
R-0 R/W-0
Internal Memory
465