M-Boot Rom Clock Settings; M-Boot Rom Boot Mode Gpio Assignments - Texas Instruments Concerto F28M35 Series Technical Reference Manual

M-Boot ROM Description
6.5.7.9 M-Boot ROM: Boot-to-OTP, OTP EntryPoint
The M-Boot ROM user OTP entry point by default is fixed to 0x68082C in OTP. This location is referred to
as M_BOOT_ROM_OTP_ENTRY_POINT in this document. If a user selects boot-to-OTP boot-mode
option using boot mode GPIO pins, then M-Boot ROM branches to location 0x68082C in OTP. User
applications which use this option must have their main() function located at this address or have a branch
to main() at this location. The boot-to-OTP option should be used if a custom boot loader is desired in the
application.
6.5.8 M-Boot ROM Clock Initialization
On this device, PLL is disabled and bypassed by default on power-up or after an external reset. M-Boot
ROM doesn't enable PLL and keeps it at its default state on power or after an external reset. M-Boot
ROM, however, configures input clocks for both the master subsystem and control subsystem by
modifying the SYSDIVSEL divider and M3SSCLK dividers as below. Please refer to the Clocking section
of the System Control and Interrupts chapter for more details on these clock dividers.
Divider
SYSDIVSEL
M3SSDIVSEL
M-Boot ROM modifies the dividers as shown in
input to reset the master subsystem, except for a debugger reset or software reset. Refer to the Resets
section in the System Control and Interrupts chapter for further discussion.
NOTE: Configuring the above dividers make a master subsystem and control subsystem RUN at the
same frequency which is equal to MAINOSC frequency selected by user. So users should be
aware of this fact while selecting a MAINOSC clock frequency. Remember that PLL is by
passed during normal boot.
6.5.9 M-Boot ROM GPIO Assignments for Each Boot Mode
The table below gives information on the GPIOs used for each boot mode on M-Boot ROM. More details
on the boot mode are provided further in this document.
M-Boot ROM Boot Peripheral
Mode
Serial Boot Mode UART0
I2C0
SSI0
Parallel Boot Mode GPIO (s)
546
ROM Code and Peripheral Booting
Table 6-7. M-Boot ROM Clock Settings
Default on Power up or on External
Divide by 8
(PLLSYSCLK = MainOscClock/8)
Divide by 4
(M3SSCLK = PLLSYSCLK/4)
Table 6-7
Table 6-8. M-Boot ROM Boot Mode GPIO Assignments
Boot Function Direction
Name for pin
UART0_RX Input
UART0_TX Ouput
I2C0_CLK Input
I2C_DATA BI-Directional
SSI0_CS Input
SSI0_CLK Input
SSI0_TX Output
SSI0_RX Input
D0 Input
D1 Input
D2 Input
D3 Input
D4 Input
D5 Input
Copyright © 2012–2019, Texas Instruments Incorporated
reset
Divide by 1
(PLLSYSCLK = MainOscClock/1)
Divide by 1
(M3SSCLK = PLLSYSCLK = MainOscClk)
for all the reset types that pull external reset
GPIO(s) used
Peripheral Mode
PA0_GPIO0 1
PA1_GPIO1 1
PB2_GPIO10 1
PB3_GPIO11 1
PA3_GPIO3 1
PA2_GPIO2 1
PA5_GPIO5 1
PA4_GPIO4 1
PA0_GPIO0 0(default)
PA1_GPIO1 0(default)
PA2_GPIO2 0(default)
PA3_GPIO3 0(default)
PA4_GPIO4 0(default)
PA5_GPIO5 0(default)
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
M-Boot ROM setting
Pin Mux Assignment
Alternate Mode Core Select
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
0(default) Master(default)
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