Message Interface Register Sets - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com
t
q
delay of bus driver
delay of receiver circuit
delay of bus line (40m)
t
Prop
t
SJW
t
TSeg1
t
TSeg2
t
Sync-Seg
bit time
tolerance for CAN_CLK
In this example, the concatenated bit time parameters are (1-1)
register is programmed to = 0x00000700.
23.12.2.3 Example for Bit Timing at low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
t
q
delay of bus driver
delay of receiver circuit
delay of bus line (40m)
t
Prop
t
SJW
t
TSeg1
t
TSeg2
t
Sync-Seg
bit time
tolerance for CAN_CLK
In this example, the concatenated bit time parameters are (4-1)
register is programmed to = 0x000034C1.

23.13 Message Interface Register Sets

The interface register sets control the CPU read and write accesses to the Message RAM. There are two
interface register sets for read or write access (IF1 and IF2) and one Interface Register Set for read
access only (IF3).
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
100 ns =
90 ns =
40 ns =
220 ns =
700 ns =
100 ns =
800 ns =
100 ns =
100 ns =
1000 ns =
0.43 % =
=
1 μs =
200 ns =
80 ns =
220 ns =
1 μs =
4 μs =
5 μs =
4 μs =
1 μs =
10 μs =
3.08 % =
=
Copyright © 2012–2019, Texas Instruments Incorporated
Message Interface Register Sets
t
CAN_CLK
2*delays = 7 • t
q
1 • t
q
t + t
Prop SJW
Information Processing Time + 1 • t
1 • t
q
t + t + t
Sync-Seg TSeg1 TSeg2
min TSeg1 Tseg2 ( , )
-----------------------------------------------------------------------
2x (13x(bit_time-TSeg2))
0,1 μs
---------------------------------------------------------- -
μs))
2x 13x( 1 s ) μ 0,1
&(8-1) &(1-1) &(1-1) , so the Bit Timing
3 4 2 6
2 • t
CAN_CLK
1 • t
q
4 • t
q
t + t
Prop SJW
Information Processing Time + 4 • t
1 • t
q
t + t + t
Sync-Seg TSeg1 TSeg2
( , )
min TSeg1 TSeg2
---------------------------------------------------------------------
2x(13x(bit_time-TSeg2))
4
μs
---------- ------------------------------------------- -
2x(13x(9 4 ))
μs -
μs
&(5-1) &(4-1) &(2-1) , so the Bit Timing
3 4 2 6
M3 Controller Area Network (CAN)
q
q
1537