Trip-Zone Flag Register (Tzflg); Trip-Zone Flag Register (Tzflg) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 7-62. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions (continued)
Bit Field
0 Reserved
15
7 6
Reserved DCBEVT2
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:7 Reserved
6 DCBEVT2
5 DCBEVT1
4 DCAEVT2
3 DCAEVT1
2 OST
1 CBC
0 INT
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Reserved
Figure 7-113. Trip-Zone Flag Register (TZFLG)
5 4
DCBEVT1 DCAEVT2
R-0 R-0
Table 7-63. Trip-Zone Flag Register (TZFLG) Field Descriptions
Value Description
Reserved
Latched Status Flag for Digital Compare Output B Event 2
0 Indicates no trip event has occurred on DCBEVT2
1 Indicates a trip event has occurred for the event defined for DCBEVT2
Latched Status Flag for Digital Compare Output B Event 1
0 Indicates no trip event has occurred on DCBEVT1
1 Indicates a trip event has occurred for the event defined for DCBEVT1
Latched Status Flag for Digital Compare Output A Event 2
0 Indicates no trip event has occurred on DCAEVT2
1 Indicates a trip event has occurred for the event defined for DCAEVT2
Latched Status Flag for Digital Compare Output A Event 1
0 Indicates no trip event has occurred on DCAEVT1
1 Indicates a trip event has occurred for the event defined for DCAEVT1
Latched Status Flag for A One-Shot Trip Event
0 No one-shot trip event has occurred.
1 Indicates a trip event has occurred on a pin selected as a one-shot trip source.
This bit is cleared by writing the appropriate value to the TZCLR register.
Latched Status Flag for Cycle-By-Cycle Trip Event
0 No cycle-by-cycle trip event has occurred.
1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The
TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip
event is still present when the CBC bit is cleared, then CBC will be immediately set again. The
specified condition on the signal is automatically cleared when the ePWM time-base counter
reaches zero (TBCTR = 0x00) if the trip condition is no longer present. The condition on the signal
is only cleared when the TBCTR = 0x00 no matter where in the cycle the CBC flag is cleared.
This bit is cleared by writing the appropriate value to the TZCLR register.
Latched Trip Interrupt Status Flag
0 Indicates no interrupt has been generated.
1 Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition.
No further EPWMx_TZINT PIE interrupts will be generated until this flag is cleared. If the interrupt
flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated.
Clearing all flag bits will prevent further interrupts.
This bit is cleared by writing the appropriate value to the TZCLR register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
DCAEVT1 OST
R-0 R-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
8
1 0
CBC INT
R-0 R-0
763