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Memory Protection Unit (MPU) Register Descriptions
25.7.2 MPU Control (MPUCTRL) Register, offset 0xD94
Note: This register can only be accessed from privileged mode.
The MPU Control (MPUCTRL) register enables the MPU, enables the default memory map background
region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
•
For privileged accesses, the default memory map is as described in the Cortex-M3 Processor chapter.
Any access by privileged software that does not address an enabled memory region behaves as
defined by the default memory map.
•
Any access by unprivileged software that does not address an enabled memory region causes a
memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of
the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to
function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then
only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same memory
attributes as if the MPU is not implemented (see the Cortex-M3 Processor chapter for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted.
Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an
exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI
exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating
with these two priorities.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-55. MPU Control (MPUCTRL) Register Field Descriptions
Bit
Field
31-3
Reserved
2
PRIVDEFEN
1
HFNMIENA
1650
Cortex-M3 Peripherals
Figure 25-48. MPU Control (MPUCTRL) Register
Reserved
R-0
Value
Description
Reserved
MPU Default Region
0
If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a
location not covered by any enabled region causes a fault.
1
If the MPU is enabled, this bit enables use of the default memory map as a background region for
privileged software accesses.
When this bit is set, the background region acts as if it is region number -1. Any region that is
defined and enabled has priority over this default map.
If the MPU is disabled, the processor ignores this bit.
MPU Enabled During Faults. This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
0
The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of
the ENABLE bit.
1
The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled and this bit is set, the resulting behavior is unpredictable
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
2
PRIVDEFEN
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
1
0
HFNMIENA
ENABLE
R/W-0
R/W-0
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