Usb Transmit Interrupt Status Register (Usbtxis), Offset 0X002; Usb Transmit Interrupt Status Register (Usbtxis); Usb Transmit Interrupt Status Register (Usbtxis) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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18.5.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002

NOTE: Use caution when reading this register. Performing a read may change bit status.
The USB transmit interrupt status 16-bit read-only register (USBTXIS) indicates which interrupts are
currently active for endpoint 0 and the transmit endpoints 1–15. The meaning of the EPn bits in this
register is based on the mode of the device. The EP1 through EP15 bits always indicate that the USB
controller is sending data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode,
the bits refer to IN endpoints. The EP0 bit is special in Host and Device modes and indicates that either a
control IN or control OUT endpoint has generated an interrupt.
Mode(s): OTG A or Host
USBTXIS is shown in
15 14 13 12
EP15 EP14 EP13 EP12
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-8. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions
Bit Field
15 EP15
14 EP14
13 EP13
12 EP12
11 EP11
10 EP10
9 EP9
8 EP8
7 EP7
SPRUH22I – April 2012 – Revised November 2019
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OTG B or Device
Figure 18-5 and described in
Figure 18-5. USB Transmit Interrupt Status Register (USBTXIS)
11 10 9
EP11 EP10 EP9
R-0 R-0 R-0
Value Description
TX Endpoint 15 Interrupt
0 No interrupt
1 The Endpoint 15 transmit interrupt is asserted.
TX Endpoint 14 Interrupt
0 No interrupt
1 The Endpoint 14 transmit interrupt is asserted.
TX Endpoint 13 Interrupt
0 No interrupt
1 The Endpoint 13 transmit interrupt is asserted.
TX Endpoint 12 Interrupt
0 No interrupt
1 The Endpoint 12 transmit interrupt is asserted.
TX Endpoint 11 Interrupt
0 No interrupt
1 The Endpoint 11 transmit interrupt is asserted.
TX Endpoint 10 Interrupt
0 No interrupt
1 The Endpoint 10 transmit interrupt is asserted.
TX Endpoint 9 Interrupt
0 No interrupt
1 The Endpoint 9 transmit interrupt is asserted.
TX Endpoint 8 Interrupt
0 No interrupt
1 The Endpoint 8 transmit interrupt is asserted.
TX Endpoint 7 Interrupt
0 No interrupt
1 The Endpoint 7 transmit interrupt is asserted.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-8.
8 7 6 5
EP8 EP7 EP6 EP5
R-0 R-0 R-0 R-0
M3 Universal Serial Bus (USB) Controller
Register Descriptions
4 3 2 1
EP4 EP3 EP2 EP1
R-0 R-0 R-0 R-0
0
EP0
R-0
1303