Epi Address Map (Epiaddrmap) Register, Offset 0X01C; Epi Address Map (Epiaddrmap) Register [Offset 0X01C]; Epi Address Map (Epiaddrmap) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

17.11.11 EPI Address Map (EPIADDRMAP) Register, offset 0x01C

This register enables address mapping. The EPI controller can directly address memory and peripherals.
In addition, the EPI controller supports address mapping to allow indirect accesses in the External RAM
and External Peripheral areas.
If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ and
EPADR bit fields should be configured for the address space. If the external device is SDRAM, SRAM, or
NOR Flash memory, the ERADR and ERSZ bit fields should be configured for the address space.
If one of the dual-chip select modes is selected (CSCFGEXT is 0x0 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFG2 register), both chip selects can share the peripheral or the memory space, or one chip
select can use the peripheral space and the other can use the memory space. In the EPIADDRMAP
register, if the EPADR field is not 0x0, the ECADR field is 0x0, and the ERADR field is 0x0, then the
address specified by EPADR is used for both chip selects, with CS0 being asserted when the MSB of the
address range is 0 and CS1 being asserted when the MSB of the address range is 1. If the ERADR field
is not 0x0, the ECADR field is 0x0, and the EPADR field is 0x0, then the address specified by ERADR is
used for both chip selects, with the MSB performing the same delineation. If both the EPADR and the
ERADR are not 0x0 and the ECADR field is 0x0, then CS0 is asserted for either address range defined by
EPADR and CS1 is asserted for either address range defined by ERADR. The two chip selects can also
be shared between the code space and memory or peripheral space. If the ECADR field is 0x1, ERADR
field is 0x0, and the EPADR field is not 0x0, then CS0 is asserted for the address range defined by
ECADR and CS1 is asserted for either address range defined by EPADR. If the ECADR field is 0x1,
EPADR field is 0x0, and the ERADR field is not 0x0, then CS0 is asserted for the address range defined
by ECADR and CS1 is asserted for either address range defined by ERADR.
If one of the quad-chip-select modes is selected (CSCFGEXT is 0x1 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFG2 register), both the peripheral and the memory space must be enabled. In the
EPIADDRMAP register, the EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is 0x0. In
this case, CS0 maps to 0x6000.0000; CS1 maps to 0x8000.0000; CS2 maps to 0xA000.0000; and CS3
maps to 0xC000.0000. The MODE field of the EPIHBnCFGn registers configures the interface for the
individual chip selects, which support ADMUX or ADNOMUX. If the CSBAUD bit is clear, all chip selects
use the mode configured in the MODE bit field of the EPIHBnCFG register.
explanation of chip select address range mappings based on which combinations of peripheral and
memory space are enabled.
Figure 17-38. EPI Address Map (EPIADDRMAP) Register [offset 0x01C]
31
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-24. EPI Address Map (EPIADDRMAP) Register Field Descriptions
Bit Field
31-12 Reserved
11-10 ECSZ
1248
External Peripheral Interface (EPI)
11 10 9
ECSZ ECADR
R/W-0 R/W-0
Value Description
Reserved
External Code Size
This field selects the size of the external code area. If the size of the external code area is larger, a
bus fault occurs. If the size of the external code area is smaller, it wraps (upper address bits
unused).
Note: When not using byte selects in Host-Bus 16, data is accessed on 2-byte boundaries. As a
result, the available address space is double the amount shown below.
0x0 256 bytes; lower address range: 0x00 to 0xFF
0x1 64KB; lower address range: 0x0000 to 0xFFFF
0x2 16MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 256MB; lower address range: 0x000.0000 to 0xFFF.FFFF
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0x0000.00
8 7 6 5
EPSZ EPADR
R/W-0x0 R/W-0x0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 17-3 gives a detailed
4 3 2 1
ERSZ ERADR
R/W-0x0 R/W-0x0
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