Msgrams; Ipc Flags And Interrupts; Ipc Msg Ram Read/Write Accesses - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.12.1 MSGRAMs

There is a dedicated 2KB MTOC message RAM (MTOCMSGRAM), from which the M3 can read/write and

the C28x can read. There is another dedicated 2KB CTOM-message RAM (CTOMMSGRAM) from which

the C28x can read/write and the M3 can read. For MTOCMSGRAM, the M3 CPU and µDMA have read

and write accesses, whereas the C28 CPU and DMA have only read access. Similarly for

CTOMMSGRAM, the C28 CPU and DMA will have read and write accesses, whereas the M3 CPU and

µDMA will have only read access. See

C28x to M3 Message RAM (2KB)

M3 to C28x Message RAM (2KB)

For safety, the master subsystem DMA's (µDMA in the master subsystem is the master for the

MTOCMSGRAM and the DMA in the control subsystem is the master for CTOMMSGRAM) write access to

a MSGRAM is made configurable using the MTOCMSGRCR and CTOMMSGRCR registers for the M3

and C28x cores, respectively. See the Internal Memory chapter for more information on these registers.

There is no hardware relationship between the IPC flags/interrupts and the message RAMs. Users can

use them together to accomplish better communication techniques between the cores/subsystems. A

protocol to use the message RAMs with the IPC flags/interrupts needs to be established in software. For

more details on MSGRAM initialization and configuration, refer to the Internal Memory chapter.

These message RAMs can be used to pass messages between the two subsystems. When the master

subsystem writes a message in MTOCMSGRAM, the M3 can use either MTOCIPC flags or interrupts to

indicate to the control subsystem that the message is ready for the C28x to read. Similarly, when the

control subsystem writes a message in CTOMMSGRAM, the C28x can use either CTOMIPC flags or

interrupts to indicate to the master subsystem that the message is ready for the M3 to read.

There are 32 IPC handshake channels from the master system to the control system and vice versa to

enable communication between the cores based on software flags. Out of these 32, four channels (1

through 4) can be enabled to generate IPC interrupts to the other core. These handshake channels can

be used along with the Message RAMs to build a software handshake mechanism between the two cores.

shows the IPC flag messaging and interrupt mechanism.

SPRUH22I – April 2012 – Revised November 2019

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Table 1-35. IPC MSG RAM Read/Write Accesses

Inter Processor Communications (IPC)

System Control and Interrupts

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