I2C Slave Data (I2Csdr), Offset 0X808; I2C Slave Interrupt Mask (I2Csimr), Offset 0X80C; I2C Slave Control/Status (I2Cscsr) Register (Write-Only); I2C Slave Data (I2Csdr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 22-26. I2C Slave Control/Status (I2CSCSR) Register (Write-Only)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-16. I2C Slave Control/Status (I2CSCSR) Register Field Descriptions (Write-Only)

22.7.3 I2C Slave Data (I2CSDR), offset 0x808

Important: This register is read-sensitive. See the register description for details.

This register contains the data to be transmitted when in the Slave Transmit state, and the data received

when in the Slave Receive state. It is shown in the figure and table below.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The I2C Slave Interrupt Mask (I2CSIMR) register controls whether a raw interrupt is promoted to a

controller interrupt. It is shown in the figure and table below.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-18. I2C Slave Interrupt Mask (I2CSIMR) Register Field Descriptions

SPRUH22I – April 2012 – Revised November 2019

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Device Active

Disables the I2C slave operation.

Enables the I2C slave operation.

Figure 22-27. I2C Slave Data (I2CSDR) Register

Table 22-17. I2C Slave Data (I2CSDR) Register Field Descriptions

Data for Transfer

This field contains the data for transfer during a slave receive or transmit operation.

Figure 22-28. I2C Slave Interrupt Mask (I2CSIMR) Register

Stop Condition Interrupt Mask

The STOPRIS interrupt is suppressed and not sent to the interrupt controller.

The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the

I2CSRIS register is set.

M3 Inter-Integrated Circuit (I2C) Interface

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