Error And Status Register (Can Es); Error And Status Register (Can Es) [Offset = 0X04]; Error And Status Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

CAN Control Registers
Table 23-5. CAN Control Register (CAN CTL) Field Descriptions (continued)
Bit Name
3 EIE
2 SIE
1 IE0
0 Init
NOTE: The Bus-Off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by
setting or resetting Init bit. If the module goes Bus-Off, it will automatically set the Init bit and
stop all bus activities. When the Init bit is cleared by the application again, the module will
then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before
resuming normal operation. At the end of the Bus-Off recovery sequence, the error counters
will be reset. After the Init bit is reset, each time when a sequence of 11 recessive bits is
monitored, a Bit0 Error code is written to the Error and Status Register, enabling the CPU to
check whether the CAN bus is stuck at dominant or continuously disturbed, and to monitor
the proceeding of the Bus-Off recovery sequence.

23.15.2 Error and Status Register (CAN ES)

The Error and Status register (CAN ES) is shown and described in the figure and table below.
31
15
Reserved
R-0
LEGEND: R = Read; S = Set by Read; C = Clear by Read; -n = value after reset
Bit Field
31-10 Reserved
9 WakeUpPnd
1546
M3 Controller Area Network (CAN)
Value Description
Error Interrupt Enable
0 Disabled - PER, BOff and EWarn bits cannot generate an interrupt.
1 Enabled - PER, BOff and EWarn bits can generate an interrupt at CAN0INT line and affect the
Interrupt Register.
Status Change Interrupt Enable
0 Disabled - WakeUpPnd, RxOk, TxOk and LEC bits cannot generate an interrupt.
1 Enabled - WakeUpPnd, RxOk, TxOk and LEC can generate an interrupt at CAN0INT line and affect
the Interrupt Register.
Interrupt line 0 Enable
0 Disabled - Module Interrupt CAN0INT is always low.
1 Enabled - Interrupts will assert line CAN0INT to one; line remains active until pending interrupts are
processed.
Initialization mode bit. This bit may be set by software, a hardware reset, or the bus-off condition.
0 Normal operation.
1 Initialization mode is entered.
Figure 23-20. Error and Status Register (CAN ES) [offset = 0x04]
10 9
Wake
UpPnd
R/C-0
Table 23-6. Error and Status Register Field Descriptions
Value Description
Reserved
Wake Up Pending This bit can be used by the CPU to identify the CAN as the source to wake up
the system.
0 No Wake Up is requested by CAN.
1 Wake up is requested. CAN has initiated a wake up of the system due to dominant CAN bus while
module power down. This bit will be reset if Error and Status Register is read.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7 6 5
PER BOff EWarn EPass
R/C-0 R-0 R-0 R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
4 3 2
RxOK TxOK LEC
R/C-0 R/C-0 R/S-111
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