Initialization And Configuration - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Initialization and Configuration

See the Micro Direct Memory Access (µDMA) chapter for more details about programming the µDMA
controller.
20.4 Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module by setting the SSI bit in the CMPCLKCR0 register.
2. Configure the pinmux.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
• For master operations, set the SSICR1 register to 0x0000.0000.
• For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
• For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
• Serial clock rate (SCR)
• Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
• Protocol mode: Freescale SPI, TI SSF
• Data size (DSS)
5. Optionally, configure the µDMA channel (see the Micro Direct Memory Access (µDMA) chapter) and
enable the DMA option(s) in the SSIDMACTL register.
6. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
• Master operation
• Freescale SPI mode (SPO=1, SPH=1)
• 1 Mbps bit rate
• 8 data bits
Assuming the system clock (CMCLK) is 20 MHz, the bit rate calculation would be:
SSIClk = (system clock) / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
1418
M3 Synchronous Serial Interface (SSI)
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SPRUH22I – April 2012 – Revised November 2019
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