16-Bit Write; 16-Bit Read - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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The ACIB buffer can store a single write operation from the digital subsystem in order to prevent the CPU
or DMA from stalling on writes. If a second write operation is initiated by the digital subsystem (before the
first write operation completes), the CPU or DMA will stall until the first write operation completes, thereby
freeing up the buffer for the second write operation.
Simplified timing diagrams for ACIB operations are shown in
approximations and may not be cycle accurate.
Clock
Ready 2-3 Cycle Sync Stall
Bus[7:0]
Size
R/W
Digital Buffer
Analog Buffer
Clock
Ready 2-3 Cycle Sync Stall
Bus[7:0]
Size
R/W
Digital Buffer
Analog Buffer
Clock
Bus[7:0] Ready 2-3 Cycle Sync Stall
Size
R/W
Digital Buffer
Analog Buffer
SPRUH22I – April 2012 – Revised November 2019
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Figure 10-3. 16-bit Write
Addr Addr Word Word
Sync Stall
15:8 7:0 15:8 7:0
Figure 10-4. 32-bit Write
Addr Addr Word 1 Word 1 Word 2
15:8 7:0 15:8 7:0 15:8
Figure 10-5. 16-bit Read
Addr Addr Word
Read Stall
15:8 7:0 15:8
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Analog Common Interface Bus (ACIB)
Figure 10-3
Word 2
Sync Stall
7:0
Word
Sync Stall
7:0
to Figure 10-9. The diagrams are
Ready
Ready
Ready
Analog Subsystem
857