4-Stage Pipeline Dma Transfer; 4-Stage Pipeline With One Read Stall (Mcbsp As Source) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Pipeline Timing and Throughput

11.3 Pipeline Timing and Throughput

The DMA consists of a 4-stage pipeline as shown in

DMA channel is configured to have the McBSP as its data source. A read of a McBSP DRR register stalls

the DMA bus for one cycle during the read portion of the transfer, as shown in

Figure 11-4. 4-Stage Pipeline With One Read Stall (McBSP as source)

In addition to the pipeline there are a few other behaviors of the DMA that affect its total throughput:

A 1-cycle delay is added at the beginning of each burst

A 1-cycle delay is added when returning from a CH1 high priority interrupt

Collisions with the CPU may add delay slots (see

Arbitration inside the analog common interface bus (ACIB) may add delay slots when reading ADC

result registers

32-bit transfers run at double the speed of a 16-bit transfer (it takes the same amount of time to

transfer a 32-bit word as it does a 16-bit word)

For example, to transfer 128 16-bit words from L2 RAM to L3 RAM a channel can be configured to

transfer 8 bursts of 16 words/burst. This will give:

8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles

If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size

is configured to 32 bits) the transfer would take:

C28 Direct Memory Access (DMA) Module

Figure 11-3. 4-Stage Pipeline DMA Transfer

11-3. The one exception to this is when a

SPRUH22I – April 2012 – Revised November 2019

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