Table of Contents
Advertisement
Exceptions and Interrupts Control
1.5.2 Master Subsystem Exceptions Handling
Table 1-8
provides information on different exceptions supported by NVIC on the master subsystem.
Exception Type
Reset
Non-Maskable
Interrupt(NMI)
Hard Fault
Memory Management
Bus Fault
Usage Fault
From the above exceptions, the NMI and bus faults are generated by the digital subsystem, whereas
memory management errors are generated internally by the M3 MPU.
Bus Fault Exceptions:
For all uncorrectable memory errors during M3 CPU reads or writes (address, parity or double data error),
HRESP-based, and HREADY-based error responses will be generated by the memory control logic.
Write Accesses:
When an HRESP-error is generated for write accesses, if the intended write was a stack push, STKERR
status will get set by the NVIC upon seeing the bus fault indication for the stack push operation. If the
application so prefers, it can treat a STKERR as a low priority exception and pend the same, except when
stacking for an exception.
Read Accesses:
For all uncorrectable errors during reads, the same HRESP-error indication will be generated. The M3
core will use this error indication in the following manner:
•
For bus errors during normal data reads, the M3 would bus fault, but the application can treat this as a
lower priority, thereby enabling a higher priority exception to be serviced by the CPU. As an example,
there may be a bus fault in a user thread and still the CPU could service an interrupt to handle critical
interrupts - the bus fault can be handled afterwards. But if the read occurs during an ISR bus fault, it
will be treated as a hard fault, since it is in code for an exception that should never fault.
•
For bus errors during stack pops, the NVIC will set the UNSTKERR status indication and the M3 will
bus fault
•
For bus errors during vector table reads, the NVIC will set VECTTBL and the M3 will bus fault. If there
is a double fault when the bus fault handler tries to read the vector, the M3 CPU will enter a LOCKUP
condition. In this condition, the M3 WDT timers will time out and issue a reset to the system.
•
For bus errors during fetches, even if the M3 sees an error response, it will not internally bus fault
96
System Control and Interrupts
Table 1-8. Master Subsystem Exceptions
Vector Number
Priority
1
-3 (highest)
2
-2
3
-1
4
Programmable
5
Programmable
6
Programmable
Copyright © 2012–2019, Texas Instruments Incorporated
Description
This exception is invoked on power up and on any other
reset. On the first instruction, Reset drops to the lowest
priority and then is called the base level of activation.
This exception is asynchronous.
This exception is caused by the assertion of the NMI
signal or by using the NVIC Interrupt Control State
register and cannot be stopped or pre-empted by any
exception but Reset. This exception is asynchronous.
Used for clock fail condition, and external M3 side GPIO
NMI input.
This exception is caused by all classes of Fault when
the fault cannot activate due to priority or the
configurable fault handler has been disabled. This
exception is synchronous.
This exception is caused by an MPU mismatch,
including access violation and no match. This exception
is synchronous.
This exception is caused by a pre-fetch fault, memory
access fault, or other address/memory related faults.
This exception is synchronous when precise and
asynchronous when imprecise. This fault can be
enabled or disabled. Generated for memory access
errors and RAM and flash uncorrectable data errors in
the device.
This exception is caused by a usage fault, such as an
undefined instruction executed or an illegal state
transition attempt. This exception is synchronous.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com
Advertisement
Chapters
Table of Contents
