Functional Description; Initialization And Configuration; Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Introduction

3.1.2 Functional Description

The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero
state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first
time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD)
register, and the timer resumes counting down from that value. Once the Watchdog Timer has been
configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer
configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset
signal has been enabled by setting the RESEN bit in the WDTCTL register, the watchdog timer asserts its
reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out,
the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that
value.
If WDTLOAD is written with a new value while the watchdog timer counter is counting, then the counter is
loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing
to the Watchdog Interrupt Clear (WDTICR) register.
The watchdog module interrupt and reset generation can be enabled or disabled as required. When the
interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state.
3.1.2.1 Register Access Timing
Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written
with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-
back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-
to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control
(WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a
write operation and set once the write completes, indicating to software that another write or read may be
started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that
WDT0 does not have this restriction as it runs off the system clock.

3.1.3 Initialization and Configuration

To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. See
the System Control chapter, Run Mode Clock Gating Control Register 0 (RCGC0) section.
The watchdog timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
3. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
4. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
5. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the watchdog timer module can be fully
locked by writing any value to the WDTLOCK register. To unlock the watchdog timer, write a value of
0x1ACC.E551.
3.2

Register Map

Table 3-1 lists the watchdog registers. The offset listed is a hexadecimal increment to the register's
address, relative to the watchdog timer base address:
• WDT0: 0x4000.0000 (ending address of 0x4000.0FFF)
• WDT1: 0x4000.1000 (ending address of 0x4000.1FFF)
Note that the watchdog timer module clock must be enabled before the registers can be programmed. See
the System Control chapter, Run Mode Clock Gating Control Register 0 (RCGC0) section.
326
M3 Watchdog Timers
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SPRUH22I – April 2012 – Revised November 2019
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