Functional Description - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 4-2. GPIO Pins and Alternate Mode Functions (continued)
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
PJ7_GPIO63/XCLKIN
The M3 GPIO Mux also contains an alternate muxing mode. The proper bits in the Alternate Peripheral
Select (GPIOAPSEL) register must be set to access these muxing options. The Digital Function
(GPIOPCTL) register can then be used to select the mux option.

4.1.3 Functional Description

Each GPIO port is a separate hardware instantiation of the same physical block (see
microcontroller contains nine ports and therefore nine of these physical GPIO blocks. Note that not all pins
may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip
peripheral modules.
SPRUH22I – April 2012 – Revised November 2019
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Digital Function (GPIOPCTL PMCx Bit Field Encoding)
MII_TXEN
MII_TXCK
SSI0Clk
MII_RXDV
SSI0Fss
MII_RXCK
SSI0Clk
MII_MDC
SSI0Fss
MII_COL
SSI1Clk
MII_CRS
SSI1Fss
MII_PHYINTRn
MII_PHYRSTn
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
U3Rx
SSI0Tx
SSI0Rx
U0Tx
U0Rx
U2Rx
U2Tx
General-Purpose Input/Output (GPIO)
Figure
4-1). The
341

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