Master And Control Subsystem Ipc Registers; Mipccounterl Register; Mipccounterh Register; Ctomipccom Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com

1.13.13 Master and Control Subsystem IPC Registers

The below registers are dual-mapped to both the master and control subsystems. For read/write registers,
see the register description to determine which subsystem has read/write or read-only access to the
register.

1.13.13.1 MIPCCOUNTERL Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-0 COUNT

1.13.13.2 MIPCCOUNTERH Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-0 COUNT

1.13.13.3 CTOMIPCCOM Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-0 COMMAND
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 1-172. MIPCCOUNTERL Register
Table 1-184. MIPCCOUNTERL Register Field Descriptions
Value Description
0 C28 IPC Counter Register. This is the low 32-bits of the free running 64 bit timestamp counter
clocked by the shared resource clock.
Figure 1-173. MIPCCOUNTERH Register
Table 1-185. MIPCCOUNTERH Register Field Descriptions
Value Description
0 M3 IPC Counter Register. This is the high 32-bits of the free running 64 bit timestamp counter
clocked by the shared resource clock.
Figure 1-174. CTOMIPCCOM Register
Table 1-186. CTOMIPCCOM Register Field Descriptions
Value Description
0 C28 TO M3 IPC Command Register. This register is defined and interpreted by software – used as
command place holder for IPC commands from the C28 to the M3 CPU. It is read/write for the C28
CPU and read only for the M3 CPU.
Copyright © 2012–2019, Texas Instruments Incorporated
COUNT
R-0
COUNT
R-0
COMMAND
R/W-0
System Control Registers
System Control and Interrupts
0
0
0
293