Configuration Options For The Dead-Band Submodule; Classical Dead-Band Operating Modes - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 7-31. Configuration Options for the Dead-Band Submodule
ePWMxA
[LOADREDMODE]
0
S4
1
0
S5
1
ePWMxB
DBCTL[IN_MODE]
Although all combinations are supported, not all are typical usage modes.
classical dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such
that EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional
modes can be achieved by changing the input signal source. The modes shown in
following categories:
• Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED)
Allows you to fully disable the dead-band submodule from the PWM signal path.
• Mode 2-5: Classical Dead-Band Polarity Settings:
These represent typical polarity configurations that should address all the active high/low modes
required by available industry power switch gate drivers. The waveforms for these typical cases are
shown in Figure
qualifier submodule to generate the signal as shown for EPWMxA.
• Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay
Finally the last two entries in
or rising-edge-delay (RED) blocks are bypassed.
Mode Mode Description
1 EPWMxA and EPWMxB Passed Through (No Delay)
2 Active High Complementary (AHC)
3 Active Low Complementary (ALC)
4 Active High (AH)
5 Active Low (AL)
SPRUH22I – April 2012 – Revised November 2019
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DBCTL
Rising Edge
Delay
DBRED
Shadow
DBRED
Active
In Out
(14-bit counter)
0
S8
1
Falling Edge
Delay
1
DBFED
Active
In Out
(14-bit counter)
S8
0
DBFED
Shadow
DBCTL[HALFCYCLE]
DBCTL[DEDB_MODE]
7-32. Note that to generate equivalent waveforms to
Table 7-15 show combinations where either the falling-edge-delay (FED)
Table 7-15. Classical Dead-Band Operating Modes
Copyright © 2012–2019, Texas Instruments Incorporated
0
RED
S2
1
0 S3
FED
1
DBCTL
[LOADFEDMODE]
DBCTL[OUT_MODE]
DBCTL[POLSEL]
Table 7-15
Figure
DBCTL[POLSEL]
S3
X
1
0
0
1
C28 Enhanced Pulse Width Modulator (ePWM) Module
ePWM Submodules
0
0
A path
S6
S1
1
1
0 S7
1
S0
1
B path
0
DBCTL[OUTSWAP]
documents some
Table 7-15 fall into the
7-32, configure the action-
DBCTL[OUT_MODE]
S2 S1 S0
X 0 0
0 1 1
1 1 1
0 1 1
1 1 1
OutA
OutB
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