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31
15
Reserved
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-12. GPTM Interrupt Clear (GPTMICR) Register Field Descriptions
Bit
Field
31-12
Reserved
11
TBMCINT
10
CBECINT
9
CBMCINT
8
TBTOCINT
7-5
Reserved
4
TAMCINT
3
RTCCINT
2
CAECINT
1
CAMCINT
0
TATOCINT
2.6.9 GPTM Timer A Interval Load (GPTMTAILR) Register, offset 0x028
The GPTM Timer A Interval Load (GPTMTAILR) register is used to load the starting count value into the
timer, when the timer is counting down. When the timer is counting up, this register sets the upper bound
for the timeout event.
When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the
upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a
16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
SPRUH22I – April 2012 – Revised November 2019
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Figure 2-13. GPTM Interrupt Clear (GPTMICR) Register
12
R-0
5
4
TAMCINT
W1C-0
Value
Description
Reserved
GPTM Timer B Mode Match Interrupt Clear.
Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the
GPTMMIS register.
GPTM Capture B Event Interrupt Clear
Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS bit in the
GPTMMIS register.
GPTM Capture B Match Interrupt Clear
Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS bit in the
GPTMMIS register.
GPTM Timer B Time-Out Interrupt Clear
Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in the
GPTMMIS register.
Reserved
GPTM Timer A Mode Match Interrupt Clear
Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the
GPTMMIS register.
GPTM RTC Interrupt Clear
Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register and the RTCMIS bit in the
GPTMMIS register.
GPTM Capture A Event Interrupt Clear
Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in the
GPTMMIS register.
GPTM Capture A Match Interrupt Clear
Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the
GPTMMIS register.
GPTM Timer A Time-Out Raw Interrupt
Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the
GPTMMIS register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11
10
TBMCINT
CBECINT
W1C-0
W1C-0
3
2
RTCCINT
CAECINT
W1C-0
W1C-0
Register Descriptions
9
8
CBMCINT
TBTOCINT
W1C-0
W1C-0
1
0
CAMCINT
TATOCINT
W1C-0
W1C-0
M3 General-Purpose Timers
16
317
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