Lx Shram Configuration Register 1 (Lxsrcr1); Lx Shram Configuration Register 1 (Lxsrcr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers
5.2.3.2

Lx SHRAM Configuration Register 1 (LxSRCR1)

31
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-47. Lx SHRAM Configuration Register 1 (LxSRCR1) Field Descriptions
Bit Field
31-11 Reserved
10 CPUWRPROTL3
9 DMAWRPROTL3
8 FETCHPROTL3
7-3 Reserved
2 CPUWRPROTC2
1 DMAWRPROTC2
0 FETCHPROTC2
466
Internal Memory
Figure 5-42. Lx SHRAM Configuration Register 1 (LxSRCR1)
Reserved
R-0
Reserved
R-0
Value Description
Reserved
CPU Write Protection L3
0 C28x CPU write allowed to L3 RAM block.
1 C28x CPU write not allowed to L3 RAM block.
DMA Write Protection L3
0 C28x DMA write allowed to L3 RAM block.
1 C28x DMA write not allowed to L3 RAM block.
CPU Fetch Protection L3
0 C28x CPU Fetch allowed from L3 RAM block.
1 C28x CPU Fetch not allowed from L3 RAM block.
Reserved
CPU Write Protection L2
0 C28x CPU write allowed to L2 RAM block.
1 C28x CPU write not allowed to L2 RAM block.
DMA Write Protection L2
0 C28x DMA write allowed to L2 RAM block.
1 C28x DMA write not allowed to L2 RAM block.
CPU Fetch Protection L2
0 C28x CPU Fetch allowed from L2 RAM block.
1 C28x CPU Fetch not allowed from L2 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11 10
CPUWRPROTL
3
R/W-0
3 2
CPUWRPROT
C2
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9 8
DMAWRPROT FETCHPROTL
L3 3
R/W-0 R/W-0
1 0
DMAWRPROT FETCHPROTC
C2 2
R/W-0 R/W-0
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