Event-Trigger Interrupt Generator - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Writing a 1 to the ETFRC[INT] bit will increment the event counter INTCNT. The counter will behave as
described above when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no
events will be detected and the ETFRC[INT] bit is also ignored. The same applies to ETINTPS[INTCNT2]
& ETINTPS[INTPRD2]
The above definition means that you can generate an interrupt on every event, on every second event, or
on every third event if using the INTCNT and INTPRD. You can generate an interrupt on every event up to
15 events if using the INTCNT2 and INTPRD2.
The INTCNT2 value can be initialized with the value from ETCNTINIT[INTINIT] based on the selection
made in ETCNTINITCTL[INTINITEN]. When ETCNTINITCTL[INTINITEN] is set, then it enables
initialization of INTCNT2 counter with contents of ETCNTINIT[INTINIT] on a SYNC event or software force
determined by ETCNTINITCTL[INTINITFRC] .
ETCLR[INT]
EPWMxINT
ETCNTINIT[INTINIT]
ETCNTINITCTL[INTINITFRC]
EPWMxSYNCI
ETCNTINITCTL[INTINITEN]
Figure 7-45 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The
enhancements include SOCASELCMP and SOCBSELCMP bit fields defined in the ETSEL register enable
CMPC and CMPD events respectively to cause a start of conversion. The ETPS[SOCPSSEL] bit field
determines whether SOCACNT2 and SOCAPRD2 take control or not. The ETPS[SOCACNT] counter and
ETPS[SOCAPRD] period values behave similarly to the interrupt generator except that the pulses are
continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a pulse is generated, but it
does not stop further pulse generation. The enable/disable bit ETSEL[SOCAEN] stops pulse generation,
but input events can still be counted until the period value is reached as with the interrupt generation logic.
The event that will trigger an SOCA and SOCB pulse can be configured separately in the
ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same events that can be
specified for the interrupt generation logic with the addition of the DCAEVT1.soc and DCBEVT1.soc event
signals from the digital compare (DC) submodule. The SOCACNT2 initialization scheme is very similar to
the interrupt generator with respective enable, value initialize and SYNC or software force options.
SPRUH22I – April 2012 – Revised November 2019
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Figure 7-44. Event-Trigger Interrupt Generator
ETFLG[INT]
ETPS[INTCNT]
Clear
Latch
Set
Generate
1 0
Interrupt
Pulse
When
Input = 1 0
ETSEL[INT]
4 4
ETPS[INTPRD]
Copyright © 2012–2019, Texas Instruments Incorporated
ETINTPS[INTCNT2]
0 1
ETPS[INTPSSEL]
ETSEL[INTSEL]
Clear CNT
4-bit ETFRC[INT]
Counter
Inc CNT
ETPS[INTPSSEL]
0 1
ETINTPS[INTPRD2]
C28 Enhanced Pulse Width Modulator (ePWM) Module
ePWM Submodules
000 0
001 CTR = Zero
CTR = PRD
010
011
CTRU = CMPA
0
100
CTRU = CMPC
1
CTRD = CMPA
0
101
CTRD = CMPC
1
CTRU = CMPB
0
110
CTRU = CMPD
1
CTRD = CMPB
0
111
CTRD = CMPD
1
ETSEL[INTSELCMP]
697