Set The Receive Word Length(S); Set The Receive Frame Length; Register Bits Used To Set The Receive Word Length(S); Register Bits Used To Set The Receive Frame Length - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Receiver Configuration

15.8.8 Set the Receive Word Length(s)

The RWDLEN1 and RWDLEN2 bit fields (see
word in phase 1 and in phase 2, respectively, of the receive data frame.
Table 15-26. Register Bits Used to Set the Receive Word Length(s)
Register Bit Name
RCR1 7-5 RWDLEN1
RCR2 7-5 RWDLEN2
15.8.8.1 Word Length Bits
Each frame can have one or two phases, depending on the value that you load into the RPHASE bit. If a
single-phase frame is selected, RWDLEN1 selects the length for every serial word received in the frame. If
a dual-phase frame is selected, RWDLEN1 determines the length of the serial words in phase 1 of the
frame and RWDLEN2 determines the word length in phase 2 of the frame.

15.8.9 Set the Receive Frame Length

The RFRLEN1 and RFRLEN2 bit fields (see
1 and in phase 2, respectively, of the receive data frame.
Table 15-27. Register Bits Used to Set the Receive Frame Length
Register Bit Name
RCR1 14-8 RFRLEN1
1082
C28 Multichannel Buffered Serial Port (McBSP)
Table 15-26) determine how many bits are in each serial
Function
Receive word length 1
Specifies the length of every serial word in phase 1 of the receive frame.
RWDLEN1 = 000
RWDLEN1 = 001
RWDLEN1 = 010
RWDLEN1 = 011
RWDLEN1 = 100
RWDLEN1 = 101
RWDLEN1 = 11X
Receive word length 2
If a dual-phase frame is selected, RWDLEN2 specifies the length of every
serial word in phase 2 of the frame.
RWDLEN2 = 000
RWDLEN2 = 001
RWDLEN2 = 010
RWDLEN2 = 011
RWDLEN2 = 100
RWDLEN2 = 101
RWDLEN2 = 11X
Table 15-27) determine how many serial words are in phase
Function
Receive frame length 1
(RFRLEN1 + 1) is the number of serial words in phase 1 of the receive
frame.
RFRLEN1 = 000 0000
RFRLEN1 = 000 0001
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RFRLEN1 = 111 1111
Copyright © 2012–2019, Texas Instruments Incorporated
8 bits
12 bits
16 bits
20 bits
24 bits
32 bits
Reserved
8 bits
12 bits
16 bits
20 bits
24 bits
32 bits
Reserved
1 word in phase 1
2 words in phase 1
|
|
128 words in phase 1
SPRUH22I – April 2012 – Revised November 2019
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Reset
Type Value
R/W 000
R/W 000
Reset
Type Value
R/W 000 0000