Reading Received Messages; Requesting New Data For A Receive Object; Storing Received Messages In Fifo Buffers; Reading From A Fifo Buffer - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Message Handling
frame, the TxRqst bit of this message object is reset. The arbitration and control bits (Identifier + IDE +
RTR + DLC) from the shift register are stored in the message object in the Message RAM and the
NewDat bit of this message object is set. The data bytes of the message object remain unchanged

23.11.9 Reading Received Messages

The CPU may read a received message any time via the IFx interface registers, the data consistency is
guaranteed by the message handler state machine.
Typically the CPU will write first 0x7F to bits [23:16] and then the number of the message object to bits
[7:0] of the Command register. That combination will transfer the whole received message from the
Message RAM into the Interface register set. Additionally, the bits NewDat and IntPnd are cleared in the
Message RAM (not in the Interface register set). The values of these bits in the Message Control register
always reflect the status before resetting the bits.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the different
matching messages has been received.
The actual value of NewDat shows whether a new message has been received since last time when this
message object was read. The actual value of MsgLst shows whether more than one message have been
received since the last time when this message object was read. MsgLst will not be automatically reset.

23.11.10 Requesting New Data for a Receive Object

By means of a remote frame, the CPU may request another CAN node to provide new data for a receive
object. Setting the TxRqst bit of a receive object will cause the transmission of a remote frame with the
receive object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be transmitted,
the TxRqst bit is automatically reset.
Setting the TxRqst bit without changing the contents of a message object requires the value 0x84 in bits
[23:16] of the Command register.

23.11.11 Storing Received Messages in FIFO Buffers

Several message objects may be grouped to form one or more FIFO Buffers. Each FIFO Buffer configured
to store received messages with a particular (group of) Identifier(s). Arbitration and Mask registers of the
FIFO Buffer's message objects are identical. The EoB (End of Buffer) bits of all but the last of the FIFO
Buffer's message objects are '0', in the last one the EoB bit is '1'.
Received messages with identifiers matching to a FIFO Buffer are stored into a message object of this
FIFO Buffer, starting with the message object with the lowest message number.
When a message is stored into a message object of a FIFO Buffer the NewDat bit of this message object
is set. By setting NewDat while EoB is '0' the message object is locked for further write accesses by the
message handler until the CPU has cleared the NewDat bit.
Messages are stored into a FIFO Buffer until the last message object of this FIFO Buffer is reached. If
none of the preceding message objects is released by writing NewDat to '0', all further messages for this
FIFO Buffer will be written into the last message object of the FIFO Buffer (EoB = '1') and therefore
overwrite previous messages in this message object.

23.11.12 Reading from a FIFO Buffer

Several messages may be accumulated in a set of message objects which are concatenated to form a
FIFO Buffer before the application program is required (in order to avoid the loss of data) to empty the
buffer. A FIFO Buffer of length N will store N-1 plus the last received message since last time it was
cleared. A FIFO Buffer is cleared by reading and resetting the NewDat bits of all its message objects,
starting at the FIFO Object with the lowest message number. This should be done in a subroutine
following the example shown in
1528
M3 Controller Area Network (CAN)
Figure 23-10.
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SPRUH22I – April 2012 – Revised November 2019
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