I2C Slave Raw Interrupt Status (I2Csris), Offset 0X810; I2C Slave Masked Interrupt Status (I2Csmis), Offset 0X814; I2C Slave Raw Interrupt Status (I2Csris) Register; I2C Slave Masked Interrupt Status (I2Csmis) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions (I2C Slave)
Table 22-18. I2C Slave Interrupt Mask (I2CSIMR) Register Field Descriptions (continued)
Bit Field
1 STARTIM
0 DATAIM

22.7.5 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810

The I2C Slave Raw Interrupt Status (I2CSRIS) register specifies whether an interrupt is pending. It is
shown in the table and figure below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-19. I2C Slave Raw Interrupt Status (I2CSRIS) Register Field Descriptions
Bit Field
31-3 Reserved
2 STOPRIS
1 STARTRIS
0 DATARIS

22.7.6 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814

The I2C Slave Masked Interrupt Status (I2CSMIS) register specifies whether an interrupt was signaled. It
is shown and described in the figure and table below.
Figure 22-30. I2C Slave Masked Interrupt Status (I2CSMIS) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1510
M3 Inter-Integrated Circuit (I2C) Interface
Value Description
Start Condition Interrupt Mask
0 The STARTRIS interrupt is suppressed and not sent to the interrupt controller.
1 The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the
I2CSRIS register is set.
Data Interrupt Mask
0 The DATARIS interrupt is suppressed and not sent to the interrupt controller.
1 The data received or data requested interrupt is sent to the interrupt controller when the DATARIS
bit in the I2CSRIS register is set
Figure 22-29. I2C Slave Raw Interrupt Status (I2CSRIS) Register
Reserved
R-0
Value Description
Reserved
Stop Condition Raw Interrupt Status. This bit is cleared by writing a 1 to the STOPIC bit in the
I2CSICR register
0 No interrupt.
1 A STOP condition interrupt is pending.
Start Condition Raw Interrupt Status. This bit is cleared by writing a 1 to the STARTIC bit in the
I2CSICR register.
0 No interrupt.
1 A START condition interrupt is pending.
Data Raw Interrupt Status. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
0 No interrupt.
1 A data received or data requested interrupt is pending.
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
3 2 1
STOPRIS STARTRIS
R-0 R-0
3 2 1
STOPMIS STARTMIS
R-0 R-0
SPRUH22I – April 2012 – Revised November 2019
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0
DATARIS
R-0
0
DATAMIS
R-0