Software Reset Control 1 (Srcr1) Register; Software Reset Control 1 (Srcr1) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.13.3.6 Software Reset Control 1 (SRCR1) Register

NOTE: Writes to this register are masked by the DC2 register.
Putting the module into reset and bringing it out of reset is done by software. When a
particular bit is set, the module goes into reset and to bring the module out of reset, software
has to again write a '0' explicitly to the register.
31 30
Reserved EPI
R-0 R/W-0
23 22
Reserved
15 14
Reserved I2C1
R-0 R/W-0
7 6
SSI3 SSI2
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-64. Software Reset Control 1 (SRCR1) Register Field Descriptions
Bit Field
31 Reserved
30 EPI
29-20 Reserved
19 TIMER3
18 TIMER2
17 TIMER1
16 TIMER0
15 Reserved
14 I2C1
13 Reserved
12 I2C0
11-8 Reserved
7 SSI3
SPRUH22I – April 2012 – Revised November 2019
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Figure 1-53. Software Reset Control 1 (SRCR1) Register
29
21 20
R-0
13 12
Reserved I2C0
R-0 R/W-0
5 4
SSI1 SSI0
R/W-0 R/W-0
Value Description
Reserved
EPI S/W Reset Control
When this bit is set, EPI module is reset. All internal data is lost and the registers are returned to
their reset states. This bit must be manually cleared after being set.
Reserved
TIMER3 S/W Reset Control
When this bit is set, GPT3 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
TIMER2 S/W Reset Control
When this bit is set, GPT2 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
TIMER1 S/W Reset Control
When this bit is set, GPT1 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
TIMER0 S/W Reset Control
When this bit is set, GPT0 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Reserved
I2C1 S/W Reset Control
When this bit is set, I2C1 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Reserved
I2C0 S/W Reset Control
When this bit is set, I2C0 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Reserved
SSI3 S/W Reset Control
When this bit is set, SSI3 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
19 18
TIMER3 TIMER2
R/W-0 R/W-0:0
11 10
Reserved
R-0
3 2
UART3 UART2
R/W-0 R/W-0
System Control and Interrupts
System Control Registers
24
17 16
TIMER1 TIMER0
R/W-0 R/W-0
9 8
1 0
UART1 UART0
R/W-0 R/W-0
193