Arbitration When Accessing Acib - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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CPU Arbitration

NOTE: If the CPU is performing a read-modify-write operation and the DMA performs a write to the

same location, the DMA write may be lost if the operation occurs in between the CPU read

and the CPU write. For this reason, it is advised not to mix such CPU accesses with DMA

accesses to the same locations.

In the case of RAM, a ping-pong scheme can be implemented to avoid the CPU and the DMA accessing

the same RAM block concurrently, thus avoiding any stalls or corruption issues.

11.4.1 Arbitration when Accessing the Analog Subsystem

The DMA read cycles to the analog subsystem must pass through the analog common interface bus

(ACIB) when accessing ADC result registers. The analog subsystem can be accessed by four masters –

C28 CPU, C28 DMA, M3 CPU, and M3 DMA. In a case where multiple masters are simultaneously

attempting to access analog subsystem peripherals, an arbitration procedure will occur. The amount of

time that DMA bus cycles may be delayed depends on how many of the other three masters are trying to

access the analog subsystem at the same time. The ACIB bus arbiter uses the round-robin algorithm to

determine which bus cycle gets through and which bus cycles have to wait at a given time.

illustrates this process.

ANALOG SUBSYSTEM

11.5 Channel Priority

Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 high-

priority mode.

11.5.1 Round-Robin Mode

In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion

C28 Direct Memory Access (DMA) Module

Figure 11-5. Arbitration when Accessing ACIB

SPRUH22I – April 2012 – Revised November 2019

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