Receive Control Registers (Rcr[1, 2]); Receive Control Register 1 (Rcr1); Receive Control Register 1 (Rcr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

McBSP Registers
Table 15-73. Serial Port Control 2 Register (SPCR2) Field Descriptions (continued)
Bit Field Value
0 XRST
0
1

15.12.5 Receive Control Registers (RCR[1, 2])

Each McBSP has two receive control registers, RCR1
registers enable you to:
• Specify one or two phases for each frame of receive data (RPHASE)
• Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (RWDLEN1,
RWDLEN2) and the number of words (RFRLEN1, RFRLEN2)
• Choose a receive companding mode, if any (RCOMPAND)
• Enable or disable the receive frame-synchronization ignore function (RFIG)
• Choose a receive data delay (RDATDLY)

15.12.5.1 Receive Control Register 1 (RCR1)

The receive control register 1 (RCR1) is shown in
15 14
Reserved
R-0
7
RWDLEN1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-74. Receive Control Register 1 (RCR1) Field Descriptions
Bit Field Value
15 Reserved 0
14-8 RFRLEN1 0-7Fh
1126
C28 Multichannel Buffered Serial Port (McBSP)
Description
Transmitter reset bit. You can use XRST to take the McBSP transmitter into and out of its reset state.
This bit has a negative polarity; XRST = 0 indicates the reset state.
To read about the effects of a transmitter reset, see
McBSP.
If you read a 0, the transmitter is in its reset state.
If you write a 0, you reset the transmitter.
If you read a 1, the transmitter is enabled.
If you write a 1, you enable the transmitter by taking it out of its reset state.
Figure 15-69. Receive Control Register 1 (RCR1)
5 4
Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Receive frame length 1 (1 to 128 words). Each frame of receive data can have one or two phases,
depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1 in
RCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dual-
phase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the frame, and
RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit RFRLEN fields
allow up to 128 words per phase. See
length. This length corresponds to the number of words or logical time slots or channels per frame-
synchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.10.2, Resetting and Initializing a
(Table 15-74) and RCR2
Figure 15-69 and described in
RFRLEN1
R/W-0
Reserved
R-0
Table 15-75 for a summary of how you determine the frame
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
(Table 15-76). These
Table 15-74.
8
0
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