Epi Host-Bus 16 Timing Extension (Epihb16Time3) Register, Offset 0X318; Epi Host-Bus 16 Timing Extension Register (Epihb16Time3) [Offset 0X318]; Epi Host-Bus 16 Timing Extension Register (Epihb16Time3) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

Advertisement

www.ti.com
Table 17-46. EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME3) Field Descriptions (continued)
Bit
Field
4
WRWSM
3-1
Reserved
0
RDWSM

17.11.34 EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Register, offset 0x318

NOTE:
The MODE field in the EPICFG register determines which configuration is enabled. For
EPIHB16TIME3 to be valid, the MODE field must be 0x3.
Figure 17-61. EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) [offset 0x318]
31
Reserved
R-0
15
14
13
12
Reserved
CAPWIDTH
R-0
R/W-0x2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-47. EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) Field Descriptions
Bit
Field
31-26
Reserved
25-24
IRDYDLY
23-14
Reserved
13-12
CAPWIDTH
11-5
Reserved
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Value
Description
CS1 Write Wait State Minus One
This bit is used with the WRWS field in EPIHB8CFG2. This field is not applicable in BURST mode.
0
No change in the number of wait state clock cycles programmed in the in WRWS field in
EPIHB8CFG2 register
1
Wait state value is now:
WRWS - 1
WRWS field is programmed in EPIHB8CFG2
Reserved
CS1 Read Wait State Minus One
Used with RDWS field in the EPIHB8CFG2 register. This field is not applicable in BURST mode.
0
No change in the number of wait state clock cycles programmed in the RDWS field of
EPIHB8CFG2
1
Wait state value is now:
RDWS - 1
RDWS field is programmed in EPIHB8CFG2
26
25
IRDYDLY
R/W-0
11
Reserved
R-0
Value
Description
Reserved
CS2 Input Ready Delay
0x0
Reserved
0x1
Stall begins one EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.
0x2
Stall begins two EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock
0x3
Stall begins three EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.
Reserved
CS2 Inter-transfer Capture Width
Controls the delay between Host-Bus transfers
0x0
Reserved
0x1
1 EPI clock
0x2
2 EPI clock
0x3
Reserved
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
24
23
5
4
WRWSM
R/W-0
Register Descriptions
Reserved
R-0
3
1
Reserved
RDWSM
R-0
R/W-0
External Peripheral Interface (EPI)
16
0
1273

Advertisement

Table of Contents
loading

Table of Contents