Epi Host-Bus 16 Timing Extension (Epihb16Time3) Register, Offset 0X318; Epi Host-Bus 16 Timing Extension Register (Epihb16Time3) [Offset 0X318]; Epi Host-Bus 16 Timing Extension Register (Epihb16Time3) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 17-46. EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME3) Field Descriptions (continued)

17.11.34 EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Register, offset 0x318

The MODE field in the EPICFG register determines which configuration is enabled. For

EPIHB16TIME3 to be valid, the MODE field must be 0x3.

Figure 17-61. EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) [offset 0x318]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-47. EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) Field Descriptions

SPRUH22I – April 2012 – Revised November 2019

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CS1 Write Wait State Minus One

This bit is used with the WRWS field in EPIHB8CFG2. This field is not applicable in BURST mode.

No change in the number of wait state clock cycles programmed in the in WRWS field in

EPIHB8CFG2 register

Wait state value is now:

WRWS field is programmed in EPIHB8CFG2

CS1 Read Wait State Minus One

Used with RDWS field in the EPIHB8CFG2 register. This field is not applicable in BURST mode.

No change in the number of wait state clock cycles programmed in the RDWS field of

Wait state value is now:

RDWS field is programmed in EPIHB8CFG2

CS2 Input Ready Delay

Stall begins one EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.

Stall begins two EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock

Stall begins three EPI clocks past iRDY low being sampled on the rising edge of the EPIO clock.

CS2 Inter-transfer Capture Width

Controls the delay between Host-Bus transfers

External Peripheral Interface (EPI)

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