Counter-Compare Control Register (Cmpctl); Counter-Compare Control Register (Cmpctl) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Registers
7.4.2 Counter-Compare Submodule Registers
Figure 7-87 through
submodule control and status registers.
15 14
Reserved
7 6
Reserved SHDWBMODE
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-37. Counter-Compare Control Register (CMPCTL) Field Descriptions
Bit Field
15-14 Reserved
13-12 LOADBSYNC
11-10 LOADASYNC
9 SHDWBFULL
8 SHDWAFULL
7 Reserved
6 SHDWBMODE
5 Reserved
4 SHDWAMODE
742
C28 Enhanced Pulse Width Modulator (ePWM) Module
Figure 7-97 and Table 7-37
Figure 7-87. Counter-Compare Control Register (CMPCTL)
13 12
LOADBSYNC
R-0
5 4
Reserved SHDWAMODE
R-0
Value Description
0 Reserved
Shadow to Active CMPB Register Load on SYNC event
00 Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE (bits 1,0) (same as
legacy)
01 Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when
SYNC occurs
10 Shadow to Active Load of CMPB:CMPBHR occurs only when a SYNC is received.
11 Reserved
Note: This bit is valid only if CMPCTL[SHDWBMODE] = 0.
Shadow to Active CMPA Register Load on SYNC event
00 Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE (bits 1,0) (same as
legacy)
01 Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when
SYNC occurs.
10 Shadow to Active Load of CMPA:CMPAHR occurs only when a SYNC is received.
11 Reserved
Note: This bit is valid only if CMPCTL[SHDWAMODE] = 0.
Counter-compare B (CMPB) Shadow Register Full Status Flag. This bit self clears once a load-
strobe occurs.
0 CMPB shadow FIFO not full yet
1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value.
Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit
write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to
CMPAHR register will not affect the flag.
This bit self clears once a load-strobe occurs.
0 CMPA shadow FIFO not full yet
1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value.
0 Reserved
Counter-compare B (CMPB) Register Operating Mode
0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1 Immediate mode. Only the active compare B register is used. All writes and reads directly access
the active register for immediate compare action
Reserved
Counter-compare A (CMPA) Register Operating Mode
0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1 Immediate mode. Only the active compare register is used. All writes and reads directly access the
active register for immediate compare action
Copyright © 2012–2019, Texas Instruments Incorporated
through Table 7-48 illustrate the counter-compare
11 10
LOADASYNC
3 2
LOADBMODE
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9 8
SHDWBFULL SHDWAFULL
1 0
LOADAMODE
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