Timerxtim Register (X = 0, 1, 2); Timerxtimh Register (X = 0, 1, 2); Cpu-Timers 0, 1, 2 Configuration And Control Registers; Timerxtim Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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The general operation of the CPU-timer is as follows: The 32-bit counter register TIMH:TIM is loaded with
the value in the period register PRDH:PRD. The counter decrements once every (TPR[TDDRH:TDDR]+1)
SYSCLKOUT cycles, where TDDRH:TDDR is the timer divider. When the counter reaches 0, a timer
interrupt output signal generates an interrupt pulse. The registers listed in
configure the timers.
Table 1-16. CPU-Timers 0, 1, 2 Configuration and Control Registers
Name Address
TIMER0TIM 0x0C00
TIMER0TIMH 0x0C01
TIMER0PRD 0x0C02
TIMER0PRDH 0x0C03
TIMER0TCR 0x0C04
TIMER0TPR 0x0C06
TIMER0TPRH 0x0C07
TIMER1TIM 0x0C08
TIMER1TIMH 0x0C09
TIMER1PRD 0x0C0A
TIMER1PRDH 0x0C0B
TIMER1TCR 0x0C0C
TIMER1TPR 0x0C0E
TIMER1TPRH 0x0C0F
TIMER2TIM 0x0C10
TIMER2TIMH 0x0C11
TIMER2PRD 0x0C12
TIMER2PRDH 0x0C13
TIMER2TCR 0x0C14
TIMER2TPR 0x0C16
TIMER2TPRH 0x0C17
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bits Field
15-0 TIM
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Size (x16) Description
1 CPU-Timer 0, Counter Register
1 CPU-Timer 0, Counter Register High
1 CPU-Timer 0, Period Register
1 CPU-Timer 0, Period Register High
1 CPU-Timer 0, Control Register
1 CPU-Timer 0, Prescale Register
1 CPU-Timer 0, Prescale Register High
1 CPU-Timer 1, Counter Register
1 CPU-Timer 1, Counter Register High
1 CPU-Timer 1, Period Register
1 CPU-Timer 1, Period Register High
1 CPU-Timer 1, Control Register
1 CPU-Timer 1, Prescale Register
1 CPU-Timer 1, Prescale Register High
1 CPU-Timer 2, Counter Register
1 CPU-Timer 2, Counter Register High
1 CPU-Timer 2, Period Register
1 CPU-Timer 2, Period Register High
1 CPU-Timer 2, Control Register
1 CPU-Timer 2, Prescale Register
1 CPU-Timer 2, Prescale Register High
Figure 1-16. TIMERxTIM Register (x = 0, 1, 2)
Table 1-17. TIMERxTIM Register Field Descriptions
CPU-Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit count
of the timer. The TIMH register holds the high 16 bits of the current 32-bit count of the timer. The TIMH:TIM
decrements by one every (TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer prescale divide-
down value. When the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded with the period
value contained in the PRDH:PRD registers. The timer interrupt (TINT) signal is generated.
Figure 1-17. TIMERxTIMH Register (x = 0, 1, 2)
Copyright © 2012–2019, Texas Instruments Incorporated
TIM
R/W-0
Description
TIMH
R/W-0
Clock Control
Table 1-16 are used to
Bit Description
Figure 1-16
Figure 1-17
Figure 1-18
Figure 1-19
Figure 1-20
Figure 1-21
Figure 1-22
Figure 1-16
Figure 1-17
Figure 1-18
Figure 1-19
Figure 1-20
Figure 1-21
Figure 1-22
Figure 1-16
Figure 1-17
Figure 1-18
Figure 1-19
Figure 1-20
Figure 1-21
Figure 1-22
System Control and Interrupts
0
0
137