Register, Offset 0X024 And 0X034; Epi Non-Blocking Read Data 0 (Epirpstd0) Register And Epi Non-Blocking Read Data 1 (Epirpstd1) Register, Offset 0X028 And 0X038; Epi Read Address 0 (Epiraddr0) Register [Offset 0X024] And Epi Read Address 1 (Epiraddr1) Register [Offset 0X034]; Epi Read Address 0 (Epiraddr0) Register And Epi Read Address 1 (Epiraddr1) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.11.13 EPI Read Address 0 (EPIRADDR0) Register and EPI Read Address 1
(EPIRADDR1) Register, offset 0x024 and 0x034
This register holds the current address value. When performing non-blocking reads via the EPIRPSTDn
registers, this register's value forms the address (when used by the mode). That is, when an EPIRPSTDn
register is written with a non-0 value, this register is used as the first address. After each read, it is
incremented by the size specified by the corresponding EPIRSIZEn register. Thus at the end of a read,
this register contains the next address for the next read. For example, if the last read was 0x20, and the
size is word, then the register contains 0x24. When a non-blocking read is cancelled, this register contains
the next address that would have been read had it not been cancelled. For example, if reading by bytes
and 0x103 had been read but not 0x104, this register contains 0x104. In this manner, the system can
determine the number of values in the NBRFIFO to drain..
Note that changing this register while a read is active has an unpredictable effect due to race condition.
Figure 17-40. EPI Read Address 0 (EPIRADDR0) Register [offset 0x024] and
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-29 Reserved
31-0 ADDR
17.11.14 EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and EPI Non-Blocking Read
Data 1 (EPIRPSTD1) Register, offset 0x028 and 0x038
This register sets up a non-blocking read via the external interface. A non-blocking read is started by
writing to this register with the count (other than 0). Clearing this register terminates an active non-
blocking read as well as cancelling any that are pending. This register should always be cleared before
writing a value other than 0; failure to do so can cause improper operation. Note that both NBR channels
can be enabled at the same time, but NBR channel 0 has the highest priority and channel 1 does not start
until channel 0 is finished.
The first address is based on the corresponding EPIRADDRn register. The address register is
incremented by the size specified by the EPIRSIZEn register after each read. If the size is less than a
word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits are
clearedhe first address is based on the corresponding EPIRADDRn register. The address register is
incremented by the size specified by the EPIRSIZEn register after each read. If the size is less than a
word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits are
cleared.
Note that all three registers may be written using one STM instruction, such as with a structure copy in
C/C++.
The data may be read from the EPIREADFIFO register after the read cycle is completed. The interrupt
mechanism is normally used to trigger the FIFO reads via ISR orµDMA.
If the countdown has not reached 0 and the NBRFIFO is full, the external interface waits until a NBRFIFO
entry becomes available to continue.
Note: if a blocking read or write is performed through the address mapped area (at 0x6000.0000 through
0xDFFF.FFFF), any current non-blocking read is paused (at the next safe boundary), and the blocking
request is inserted. After completion of any blocking reads or writes, the non-blocking reads continue from
where they were paused.
SPRUH22I – April 2012 – Revised November 2019
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EPI Read Address 1 (EPIRADDR1) Register [offset 0x034]
R/W-0x0000.0000
Table 17-26. EPI Read Address 0 (EPIRADDR0) Register and
EPI Read Address 1 (EPIRADDR1) Register Field Descriptions
Value Description
Reserved
Current Address
Next address to read
Copyright © 2012–2019, Texas Instruments Incorporated
ADDR
External Peripheral Interface (EPI)
Register Descriptions
0
1251