Register Summary; Data Receive Registers (Drr[1,2]); Mcbsp Register Summary - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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15.12.1 Register Summary

Name McBSP-A
Address
Data Registers, Receive, Transmit
DRR2 0x5000
DRR1 0x5001
DXR2 0x5002
DXR1 0x5003
McBSP Control Registers
SPCR2 0x5004
SPCR1 0x5005
RCR2 0x5006
RCR1 0x5007
XCR2 0x5008
XCR1 0x5009
SRGR2 0x500A
SRGR1 0x500B
Multichannel Control Registers
MCR2 0x500C
MCR1 0x500D
RCERA 0x500E
RCERB 0x500F
XCERA 0x5010
XCERB 0x5011
PCR 0x5012
RCERC 0x5013
RCERD 0x5014
XCERC 0x5015
XCERD 0x5016
RCERE 0x5017
RCERF 0x5018
XCERE 0x5019
XCERF 0x501A
RCERG 0x501B
RCERH 0x501C
XCERG 0x501D
XCERH 0x501E
MFFINT 0x5023

15.12.2 Data Receive Registers (DRR[1,2])

The CPU or the DMA controller reads received data from one or both of the data receive registers (see
Figure 15-65). If the serial word length is 16 bits or smaller, only DRR1 is used. If the serial length is larger
than 16 bits, both DRR1 and DRR2 are used and DRR2 holds the most significant bits. Each frame of
receive data in the McBSP can have one phase or two phases, each with its own serial word length.
SPRUH22I – April 2012 – Revised November 2019
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Table 15-71. McBSP Register Summary
Type Reset Value Description
R 0x0000 McBSP Data Receive Register 2
R 0x0000 McBSP Data Receive Register 1
W 0x0000 McBSP Data Transmit Register 2
W 0x0000 McBSP Data Transmit Register 1
R/W 0x0000 McBSP Serial Port Control Register 2
R/W 0x0000 McBSP Serial Port Control Register 1
R/W 0x0000 McBSP Receive Control Register 2
R/W 0x0000 McBSP Receive Control Register 1
R/W 0x0000 McBSP Transmit Control Register 2
R/W 0x0000 McBSP Transmit Control Register 1
R/W 0x0000 McBSP Sample Rate Generator Register 2
R/W 0x0000 McBSP Sample Rate Generator Register 1
R/W 0x0000 McBSP Multichannel Register 2
R/W 0x0000 McBSP Multichannel Register 1
R/W 0x0000 McBSP Receive Channel Enable Register Partition A
R/W 0x0000 McBSP Receive Channel Enable Register Partition B
R/W 0x0000 McBSP Transmit Channel Enable Register Partition A
R/W 0x0000 McBSP Transmit Channel Enable Register Partition B
R/W 0x0000 McBSP Pin Control Register
R/W 0x0000 McBSP Receive Channel Enable Register Partition C
R/W 0x0000 McBSP Receive Channel Enable Register Partition D
R/W 0x0000 McBSP Transmit Channel Enable Register Partition C
R/W 0x0000 McBSP Transmit Channel Enable Register Partition D
R/W 0x0000 McBSP Receive Channel Enable Register Partition E
R/W 0x0000 McBSP Receive Channel Enable Register Partition F
R/W 0x0000 McBSP Transmit Channel Enable Register Partition E
R/W 0x0000 McBSP Transmit Channel Enable Register Partition F
R/W 0x0000 McBSP Receive Channel Enable Register Partition G
R/W 0x0000 McBSP Receive Channel Enable Register Partition H
R/W 0x0000 McBSP Transmit Channel Enable Register Partition G
R/W 0x0000 McBSP Transmit Channel Enable Register Partition H
R/W 0x0000 McBSP Interrupt Enable Register
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C28 Multichannel Buffered Serial Port (McBSP)
McBSP Registers
1119