Epi Host-Bus 16 Configuration 3 (Epihb16Cfg3), Offset 0X308; Epi Host-Bus 16 Configuration 3 Register (Epihb16Cfg3) [Offset 0X308]; Epi Host-Bus 16 Configuration 3 Register (Epihb16Cfg3) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions
Table 17-38. EPI Host-Bus 8 Configuration 3 Register (EPIHB8CFG3) Field Descriptions (continued)
Bit Field
1-0 MODE

17.11.26 EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308

NOTE: The MODE field in the EPICFG register determines which configuration is enabled. For
EPIHB16CFG3 to be valid, the MODE field must be 0x3.
Figure 17-53. EPI Host-Bus 16 Configuration 3 Register (EPIHB16CFG3) [offset 0x308]
31
Reserved
R-0
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-39. EPI Host-Bus 16 Configuration 3 Register (EPIHB16CFG3) Field Descriptions
Bit Field
31-22 Reserved
21 WRHIGH
20 RDHIGH
19 ALEHIGH
18-17 Reserved
1264
External Peripheral Interface (EPI)
Value Description
CS2 Host Bus Sub-Mode
This field determines which Host Bus 8 sub-mode to use for CS2 in multiple chip-select mode.
Sub-mode use is determined by the connected external peripheral. See
on how this bit field affects the operation of the EPI signals.
Note: The CSBAUD bit must be set to enable this CS2 MODE field. If CSBAUD is clear, all chip
selects use the MODE configuration defined in the EPIHB8CFG register.
0x0 ADMUX – AD[7:0]
Data and Address are muxed.
0x1 ADNONMUX – D[7:0]
Data and address are separate.
0x2 Continuous Read - D[7:0]
This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE
strobing.
0x3 Reserved
22
R-0
Value Description
Reserved
CS2 WRITE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2 .
0 The WRITE strobe for CS2 accesses is WR (active Low).
1 The WRITE strobe for CS2 accesses is WR (active High).
CS2 READ Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0 The READ strobe for CS2 accesses is RD (active Low).
1 The READ strobe for CS2 accesses is RD (active High).
CS2 ALE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0 The address latch strobe for CS2 accesses is ADV (active Low).
1 The address latch strobe for CS2 accesses is ALE (active High).
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
21 20
WRHIGH RDHIGH
R/W-0 R/W-0
8 7 6 5
WRWS
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 17-6 for information
19 18 17
ALEHIGH Reserved
R/W-1 R-0
2 1
Reserved MODE
R-0 R/W-0
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16
BURS
T
R/W-0
0