Register Descriptions
18.5.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
The USB receive FIFO start address 16-bit register (USBRXFIFOADD) controls the start address of the
selected receive endpoint FIFOs.
Mode(s):
OTG A or Host
USBRXFIFOADDR is shown in
Figure 18-22. USB Receive FIFO Start Address Register (USBRXFIFOADDR)
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-25. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions
Bit
Field
Value
15-9
Reserved
8-0
ADDR
1324
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-22
9
Description
0
Reserved
Start Address of the endpoint FIFO in units of 8 bytes.
0h
0
1h
8
2h
16
3h
24
4h
32
5h
40
6h
48
7h
56
8h
64
..
..
1FFh
4095
Copyright © 2012–2019, Texas Instruments Incorporated
and described in
Table
18-25.
8
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
ADDR
R/W-0
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